csl_nandhwcontrol.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */ 

/** @file csl_nandHwControl.c
 *
 *    @brief    File for functional layer of CSL API @a CSL_nandHwControl()
 *
 *  Description
 *    - The @a CSL_nandHwControl() function definition & it's associated
 *      functions
 *
 *  Path: \\(CSLPATH)\\ipmodules\\nfc\\src
 *
 *  Modification 1
 *    - Modified on: 28/6/2004
 *    - Reason: created the sources
 *
 *  @date 28th June, 2004
 *  @author Santosh Narayanan.
 */

/* =============================================================================
 *  Revision History
 *  ===============
 *  11-Oct-2004 Nsr Added the function header for function CSL_nandHwControl()
 *  03-sep-2004 Nsr Updated the CSL_nandHwControl to call respective functions.
 *
 * =============================================================================
 */

/** @brief Takes a command with an optional argument & implements it.
 */
 
#include <csl_nand.h>
#include <csl_nandAux.h>

/** ============================================================================
 *   @n@b CSL_nandHwControl
 *
 *   @b Description
 *   @n Takes a command of NAND with an optional argument & implements it.
 *
 *   @b Arguments
 * @verbatim
            hNand           Handle to the NAND instance

            cmd             The command to this API indicates the action to be
                            taken on NAND.

            arg             An optional argument.
   @endverbatim
 *
 *   <b> Return Value </b>  CSL_Status
 *   @li                    CSL_SOK             - Status info return successful.
 *   @li                    CSL_ESYS_BADHANDLE  - Invalid handle
 *   @li                    CSL_ESYS_INVCMD     - Invalid command
 *   @li                    CSL_ESYS_FAIL       - Invalid instance number
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  None
 *
 *   @b Modifies
 *   @n The hardware registers of NAND.
 *
 *   @b Example
 *   @verbatim
        CSL_NandHandle         hNand;
        CSL_NandHwControlCmd   cmd;
        void                  arg;

        status = CSL_nandHwControl (hNand, cmd, &arg);

     @endverbatim
 * =============================================================================
 */
#pragma CODE_SECTION (CSL_nandHwControl, ".text:csl_section:nand");
CSL_Status  CSL_nandHwControl(
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle                         hNand,
    /** The command to this API indicates the action to be taken
     */
    CSL_NandHwControlCmd                   cmd,
    /** An optional argument @a void* casted
     */
    void                                   *arg
)
{
    CSL_Status status = CSL_SOK;
    
    if( hNand == NULL){
        status=CSL_ESYS_BADHANDLE;
        return status;
    }
    
    if( arg == NULL){
        status=CSL_ESYS_INVPARAMS;
        return status;
    }

    switch(cmd){
        case CSL_NAND_CMD_WR_ENABLE:
            CSL_nandWrEnable (hNand ,(*(Uint16*)arg));
            break;
        
        case CSL_NAND_CMD_WR_DISABLE:
            CSL_nandWrDisable (hNand, (*(Uint16*)arg));
            break;
        
        case CSL_NAND_CMD_LT_ENABLE:
            CSL_nandLtEnable (hNand);
            break;
        
        case CSL_NAND_CMD_LT_DISABLE:
            CSL_nandLtDisable (hNand);
            break;
        
        case CSL_NAND_CMD_AT_ENABLE:
            CSL_nandAtEnable (hNand);
            break;
        
        case CSL_NAND_CMD_AT_DISABLE:
            CSL_nandAtDisable (hNand);
            break;
        
        case CSL_NAND_CMD_CS5_ECC_START:
            CSL_nandCs5EccStart (hNand);
            break;
        
        case CSL_NAND_CMD_CS4_ECC_START:
            CSL_nandCs4EccStart (hNand);
            break;
        
        case CSL_NAND_CMD_CS3_ECC_START:
            CSL_nandCs3EccStart (hNand);
            break;
        
        case CSL_NAND_CMD_CS2_ECC_START:
            CSL_nandCs2EccStart (hNand);
            break;
        
        case CSL_NAND_CMD_CS5_NAND_ENABLE:
            CSL_nandCs5NandEnable (hNand);
            break;
        
        case CSL_NAND_CMD_CS5_NAND_DISABLE:
            CSL_nandCs5NandDisable (hNand);
            break;
        
        case CSL_NAND_CMD_CS4_NAND_ENABLE:
            CSL_nandCs4NandEnable (hNand);
            break;
        
        case CSL_NAND_CMD_CS4_NAND_DISABLE:
            CSL_nandCs4NandDisable (hNand);
            break;
        
        case CSL_NAND_CMD_CS3_NAND_ENABLE:
            CSL_nandCs3NandEnable (hNand);
            break;
        
        case CSL_NAND_CMD_CS3_NAND_DISABLE:
            CSL_nandCs3NandDisable (hNand);
            break;
        
        case CSL_NAND_CMD_CS2_NAND_ENABLE:
            CSL_nandCs2NandEnable (hNand);
            break;
        
        case CSL_NAND_CMD_CS2_NAND_DISABLE:
            CSL_nandCs2NandDisable (hNand);
            break;
        
        case CSL_NAND_CMD_IODFT_SET_TLEC:
            CSL_nandIodftSetTlec ( hNand , (*(Uint16*)arg));
            break;
        
        case CSL_NAND_CMD_IODFT_MISR_ON:
            CSL_nandIodftMisrOn ( hNand, (*(Uint16*)arg));
            break;
        
        case CSL_NAND_CMD_IODFT_MISR_OFF:
            CSL_nandIodftMisrOff (hNand);
            break;
        
        case CSL_NAND_CMD_IODFT_OPGLD:
            CSL_nandIodftOpgld (hNand);
            break;
        
        case CSL_NAND_CMD_IODFT_MMS_OP_REG:
            CSL_nandIodftMmsOpReg (hNand);        
            break;
        
        case CSL_NAND_CMD_IODFT_MMS_INP_CAP:
            CSL_nandIodftMmsInpCap (hNand);
            break;
        
        case CSL_NAND_CMD_IODFT_ESEL_TEST:
            CSL_nandIodftEselTest (hNand);
            break;
        
        case CSL_NAND_CMD_IODFT_ESEL_NORMAL:
            CSL_nandIodftEselNormal (hNand);
            break;
        
        case CSL_NAND_CMD_IODFT_TOEN_ENABLE:
            CSL_nandIodftToenEnable (hNand);
            break;
        
        case CSL_NAND_CMD_IODFT_TOEN_DISABLE:
            CSL_nandIodftToenDisable (hNand);
            break;
        
        case CSL_NAND_CMD_IODFT_SET_MISR_STATE:
            CSL_nandIodftSetMisrState ( hNand,(*(Uint16*)arg));
            break;
        
        case CSL_NAND_CMD_IODFT_SET_PATTERN_CODE:
            CSL_nandIodftSetPatternCode ( hNand, (*(Uint16*)arg));
            break;
        
        case CSL_NAND_CMD_IODFT_FUNC_MODE:
            CSL_nandIodftFuncMode (hNand);        
            break;
        
        case CSL_NAND_CMD_IODFT_MODE:
            CSL_nandIodftMode (hNand);
            break;
        
        default:
            status = CSL_ESYS_INVCMD ;
            break;
    }
    
    return status;
}