csl_nandhwsetup.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */ 

/** @file csl_nandHwSetup.c
 *
 *  @brief    File for functional layer of CSL API @a CSL_nandHwSetup()
 *
 *  Description
 *    - The @a CSL_nandHwSetup() function definition & it's associated
 *      functions
 *
 *  Path: \\(CSLPATH)\\ipmodules\\nfc\\src
 *
 *  Modification 1
 *    - Modified on: 28/6/2004
 *    - Reason: created the sources
 *
 *  @date 28th June, 2004
 *  @author Santosh Narayanan.
 */

#include <csl_nand.h>

/** ============================================================================
 *   @n@b CSL_nandHwSetup
 *
 *   @b Description
 *   @n It configures the nand registers as per the values passed
 *      in the hardware setup structure.
 *
 *   @b Arguments
 *   @verbatim
            hNand           Handle to the NAND instance
            hwSetup         Pointer to harware setup structure
     @endverbatim
 *
 *   <b> Return Value </b>  CSL_Status
 *   @li                    CSL_SOK             - Hardware setup successful.
 *   @li                    CSL_ESYS_BADHANDLE  - Invalid handle
 *   @li                    CSL_ESYS_INVPARAMS  - Hardware structure is not
                                                  properly initialized
 *
 *   @b Modifies
 *   @n The hardware registers of NAND.
 *
 *   @b Example
 *   @verbatim
        CSL_NandHandle    hNand;
        CSL_NandObj       nandObj;
        CSL_NandHwSetup   hwSetup;
        CSL_status       status;

        ...

        hNand = CSL_nandOpen (&nandObj, CSL_NAND_PRIMARY, NULL, &status);

        status = CSL_nandHwSetup(hNand, &hwSetup);
 *   @endverbatim
 * =============================================================================
 */
#pragma CODE_SECTION (CSL_nandHwSetup, ".text:csl_section:nand");
CSL_Status  CSL_nandHwSetup(
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call 
     */
    CSL_NandHandle                         hNand,
    /** Pointer to setup structure which contains the
     *  information to program NAND to a useful state 
     */
    CSL_NandHwSetup                        *setup
)
{
    CSL_Status status = CSL_SOK;
 
    if( hNand == NULL)
        return CSL_ESYS_BADHANDLE;
        
    if( setup == NULL)
        return CSL_ESYS_INVPARAMS;

    /** 
     * Setup the configuration parameters in the Async Wait Cycle
     * Config Register
     */
    hNand->regs->AWCCR 
         = (hNand->regs->AWCCR & 0x0F00FF00)
           |(CSL_FMK(NAND_AWCCR_WP3, setup->asyncWaitCycleConfig->wp3)
           |CSL_FMK(NAND_AWCCR_WP2, setup->asyncWaitCycleConfig->wp2)
           |CSL_FMK(NAND_AWCCR_WP1, setup->asyncWaitCycleConfig->wp1)
           |CSL_FMK(NAND_AWCCR_WP0, setup->asyncWaitCycleConfig->wp0)
           |CSL_FMK(NAND_AWCCR_CS3WAIT, setup->asyncWaitCycleConfig->cs3Wait)
           |CSL_FMK(NAND_AWCCR_CS2WAIT, setup->asyncWaitCycleConfig->cs2Wait)
           |CSL_FMK(NAND_AWCCR_CS1WAIT, setup->asyncWaitCycleConfig->cs1Wait)
           |CSL_FMK(NAND_AWCCR_CS0WAIT, setup->asyncWaitCycleConfig->cs0Wait)
           |CSL_FMK(NAND_AWCCR_MEWC, setup->asyncWaitCycleConfig->maxExtWait));

       /* Setup the Async Bank Registers */
    hNand->regs->AB1CR 
         = (CSL_FMK(NAND_AB1CR_SS, setup->asyncBank1Config->selectStrobe)
           |CSL_FMK(NAND_AB1CR_EW, setup->asyncBank1Config->extWait)
           |CSL_FMK(NAND_AB1CR_W_SETUP, setup->asyncBank1Config->writeSetup)
           |CSL_FMK(NAND_AB1CR_W_STROBE, setup->asyncBank1Config->writeStrobe)
           |CSL_FMK(NAND_AB1CR_W_HOLD, setup->asyncBank1Config->writeHold)
           |CSL_FMK(NAND_AB1CR_R_SETUP, setup->asyncBank1Config->readSetup)
           |CSL_FMK(NAND_AB1CR_R_STROBE, setup->asyncBank1Config->readStrobe)
           |CSL_FMK(NAND_AB1CR_R_HOLD, setup->asyncBank1Config->readHold)
           |CSL_FMK(NAND_AB1CR_TA, setup->asyncBank1Config->turnAround)
           |CSL_FMK(NAND_AB1CR_ASIZE, setup->asyncBank1Config->asyncSize));

    hNand->regs->AB2CR
         = (CSL_FMK(NAND_AB2CR_SS, setup->asyncBank2Config->selectStrobe)
           |CSL_FMK(NAND_AB2CR_EW, setup->asyncBank2Config->extWait)
           |CSL_FMK(NAND_AB2CR_W_SETUP, setup->asyncBank2Config->writeSetup)
           |CSL_FMK(NAND_AB2CR_W_STROBE, setup->asyncBank2Config->writeStrobe)
           |CSL_FMK(NAND_AB2CR_W_HOLD, setup->asyncBank2Config->writeHold)
           |CSL_FMK(NAND_AB2CR_R_SETUP, setup->asyncBank2Config->readSetup)
           |CSL_FMK(NAND_AB2CR_R_STROBE, setup->asyncBank2Config->readStrobe)
           |CSL_FMK(NAND_AB2CR_R_HOLD, setup->asyncBank2Config->readHold)
           |CSL_FMK(NAND_AB2CR_TA, setup->asyncBank2Config->turnAround)
           |CSL_FMK(NAND_AB2CR_ASIZE, setup->asyncBank2Config->asyncSize));
  
    hNand->regs->AB3CR
         = (CSL_FMK(NAND_AB3CR_SS, setup->asyncBank3Config->selectStrobe)
           |CSL_FMK(NAND_AB3CR_EW, setup->asyncBank3Config->extWait)
           |CSL_FMK(NAND_AB3CR_W_SETUP, setup->asyncBank3Config->writeSetup)
           |CSL_FMK(NAND_AB3CR_W_STROBE, setup->asyncBank3Config->writeStrobe)
           |CSL_FMK(NAND_AB3CR_W_HOLD, setup->asyncBank3Config->writeHold)
           |CSL_FMK(NAND_AB3CR_R_SETUP, setup->asyncBank3Config->readSetup)
           |CSL_FMK(NAND_AB3CR_R_STROBE, setup->asyncBank3Config->readStrobe)
           |CSL_FMK(NAND_AB3CR_R_HOLD, setup->asyncBank3Config->readHold)
           |CSL_FMK(NAND_AB3CR_TA, setup->asyncBank3Config->turnAround)
           |CSL_FMK(NAND_AB3CR_ASIZE, setup->asyncBank3Config->asyncSize));

    hNand->regs->AB4CR
         = (CSL_FMK(NAND_AB4CR_SS, setup->asyncBank4Config->selectStrobe)
           |CSL_FMK(NAND_AB4CR_EW, setup->asyncBank4Config->extWait)
           |CSL_FMK(NAND_AB4CR_W_SETUP, setup->asyncBank4Config->writeSetup)
           |CSL_FMK(NAND_AB4CR_W_STROBE, setup->asyncBank4Config->writeStrobe)
           |CSL_FMK(NAND_AB4CR_W_HOLD, setup->asyncBank4Config->writeHold)
           |CSL_FMK(NAND_AB4CR_R_SETUP, setup->asyncBank4Config->readSetup)
           |CSL_FMK(NAND_AB4CR_R_STROBE, setup->asyncBank4Config->readStrobe)
           |CSL_FMK(NAND_AB4CR_R_HOLD, setup->asyncBank4Config->readHold)
           |CSL_FMK(NAND_AB4CR_TA, setup->asyncBank4Config->turnAround)
           |CSL_FMK(NAND_AB4CR_ASIZE, setup->asyncBank4Config->asyncSize));

      /* Setup the NAND FLASH Control configuration */
    hNand->regs->NANDFCR 
         = (hNand->regs->NANDFCR & 0xFFFFFFF0) 
           |(CSL_FMK(NAND_NANDFCR_CS5NAND, setup ->nandFlashControl->cs5nand)
           |CSL_FMK(NAND_NANDFCR_CS4NAND, setup ->nandFlashControl->cs4nand)
           |CSL_FMK(NAND_NANDFCR_CS3NAND, setup ->nandFlashControl->cs3nand)
           |CSL_FMK(NAND_NANDFCR_CS2NAND, setup ->nandFlashControl->cs2nand));
    
    hNand->regs->CE0DATA =  setup->nandBaseAddress + 0x100;
    hNand->regs->CE0ALE  =  setup->nandBaseAddress + 0x104;
    hNand->regs->CE0CLE  =  setup->nandBaseAddress + 0x108;
    
    hNand->regs->CE1DATA =  setup->nandBaseAddress + 0x110;
    hNand->regs->CE1ALE  =  setup->nandBaseAddress + 0x114;
    hNand->regs->CE1CLE  =  setup->nandBaseAddress + 0x118;
    
    hNand->regs->CE2DATA =  setup->nandBaseAddress + 0x120;
    hNand->regs->CE2ALE  =  setup->nandBaseAddress + 0x124;
    hNand->regs->CE2CLE  =  setup->nandBaseAddress + 0x128;
    
    hNand->regs->CE3DATA =  setup->nandBaseAddress + 0x130;
    hNand->regs->CE3ALE  =  setup->nandBaseAddress + 0x134;
    hNand->regs->CE3CLE  =  setup->nandBaseAddress + 0x138;
    
    return status;
}