📄 csl_wdt.h
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/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** @file csl_wdt.h
*
*
* @brief WDT functional layer API header file
*
* Path: \\(CSLPATH)\\ipmodules\\wdt\\src
*
*/
/** @mainpage WDT CSL 3.x
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to identify a set of common CSL APIs for
* the WDT module across various devices. The CSL developer is expected to
* refer to this document while designing APIs for these modules. Some of the
* listed APIs may not be applicable to a given WDT module. While other cases
* this list of APIs may not be sufficient to cover all the features of a
* particular WDT Module. The CSL developer should use his discretion designing
* new APIs or extending the existing ones to cover these.
*
* @subsection aaa Terms and Abbreviations
* -# CSL: Chip Support Library
* -# API: Application Programmer Interface
*
* @subsection References
* -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02
*
*/
/* =============================================================================
* Revision History
* ===============
* 28-April-2005 HMM Added one control command for WDT mode setup.
* 14-April-2005 HMM updated, independent load, CLK variable added and Variable
* name is changed.
* 01-Sep-2004 Hmm File created.
* =============================================================================
*/
#ifndef _CSL_WDT_H_
#define _CSL_WDT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <soc.h>
#include <cslr_wdt.h>
/**
* watchdog timer global typedef declarations
*/
/**
* @brief This enum describes the commands used to control the watchdog timer
* through CSL_wdtHwControl ()
*/
typedef enum {
/**
* @brief Loads the watchdog Timer Period Register 12
* @param Uint32 *
*/
CSL_WDT_CMD_LOAD12 = 0,
/**
* @brief Loads the watchdog Timer Period Register 34
* @param Uint32 *
*/
CSL_WDT_CMD_LOAD34 = 1,
/**
* @brief Enable the watchdog timer
* @param None
*/
CSL_WDT_CMD_START = 2,
/**
* @brief Idle allow the watchdog timer into idle mode
* @param None
*/
CSL_WDT_CMD_ALLOWIDLE = 3,
/**
* @brief Disallow the watchdog timer into idle mode
* @param None
*/
CSL_WDT_CMD_DISALLOWIDLE = 4,
/**
* @brief set the watchdog timer working state
* @param Uint16
*/
CSL_WDT_CMD_LOADKEY = 5,
/**
* @brief set the watchdog timer mode
* @param CSL_WdtTmrMode
*/
CSL_WDT_CMD_WDT_MODE = 6
} CSL_WdtHwControlCmd;
/**
* @brief This enum describes the commands used to get status of various
* parameters of the watchdog timer. These values are used in
* CSL_wdtGetHwStatus ()
*/
typedef enum {
/**
* @brief Gets the current value of the watchdog timer TIMx register
* @param Uint32 pointer
*/
CSL_WDT_QUERY_COUNT12 = 0,
/**
* @brief Gets the current value of the watchdog timer TIMx register
* @param Uint32 pointer
*/
CSL_WDT_QUERY_COUNT34 = 1,
/**
* @brief This query command returns the status
* about whether the watchdog timer is running or stopped
*
* @param CSL_WdtFlagBitStatus
*/
CSL_WDT_QUERY_WDFLAG_STAT = 2,
/**
* @brief This query command returns the watchdog timer's
* Peripheral Identification number
* @param CSL_WdtPidNumber
*/
CSL_WDT_QUERY_PID_NUMBER = 3
} CSL_WdtHwStatusQuery;
/**
* @brief The enum describes the modes of the watchdog timer. The watchdog
* timer can be programmed in general purpose timer mode or in watchdog
* timer mode
*/
typedef enum{
/** The timer is disabled and maintains current value */
CSL_WDT_ENAMODE_DISABLE = CSL_WDT_TCR_ENAMODE12_DISABLED,
/** The timer is enabled one time */
CSL_WDT_ENAMODE_ENABLE = CSL_WDT_TCR_ENAMODE12_ONCE,
/** The timer is enabled continuously */
CSL_WDT_ENAMODE_CONTINU = CSL_WDT_TCR_ENAMODE12_CONTINUOUS
}CSL_WdtTcr12Enamode;
/**
* @brief The enum describes the Pulse widths of the watchdog timer.
*/
typedef enum{
/** One timer clock cycle */
CSL_WDT_PW_ONECLK = CSL_WDT_TCR_PWID12_INACTIVE_1CYCLE,
/** One timer clock cycle */
CSL_WDT_PW_TWOCLK = CSL_WDT_TCR_PWID12_INACTIVE_2CYCLES,
/** One timer clock cycle */
CSL_WDT_PW_THREECLK = CSL_WDT_TCR_PWID12_INACTIVE_3CYCLES,
/** One timer clock cycle */
CSL_WDT_PW_FOURCLK = CSL_WDT_TCR_PWID12_INACTIVE_4CYCLES
}CSL_WdtTcr12PulseWidth;
/**
* @brief The enum describes the Timer modes of the watchdog timer.
*/
typedef enum{
/** The timer is in 64-bit GP timer mode */
CSL_WDT_TIMMODE_GPT = CSL_WDT_TGCR_TIMMODE_64BIT_GPTIM,
/** The timer is in dual 32-bit timer, unchained mode */
CSL_WDT_TIMMODE_DUAL_UNCHAINED = CSL_WDT_TGCR_TIMMODE_32BIT_DUAL,
/** The timer is in 64-bit Watchdog timer mode */
CSL_WDT_TIMMODE_WDT = CSL_WDT_TGCR_TIMMODE_64BIT_WDTIM,
/** The timer is in dual 32-bit timer, chained mode */
CSL_WDT_TIMMODE_DUAL_CHAINED = CSL_WDT_TGCR_TIMMODE_32BIT_CHAINED
}CSL_WdtTmrMode;
/**
* @brief The enum describes the States of the watchdog timer TIM34.
*/
typedef enum{
/** timer TIM34 is in reset */
CSL_WDT_TIM34RS_RESET = CSL_WDT_TGCR_TIM34RS_RESETVAL,
/** timer TIM34 is not in reset. TIM34 can be used as a 32-bit timer */
CSL_WDT_TIM34RS_ACTIVE = CSL_WDT_TGCR_TIM34RS_NOT_IN_RESET
}CSL_WdtTmr34State;
/**
* @brief The enum describes the States of the watchdog timer TIM12.
*/
typedef enum{
/** timer TIM12 is in reset */
CSL_WDT_TIM12RS_RESET = CSL_WDT_TGCR_TIM12RS_RESETVAL,
/** timer TIM34 is not in reset. TIM34 can be used as a 32-bit timer */
CSL_WDT_TIM12RS_ACTIVE = CSL_WDT_TGCR_TIM12RS_NOT_IN_RESET
}CSL_WdtTmr12State;
/**
* @brief The enum describes the Flag Bit Status of the watchdog timer.
*/
typedef enum{
/** No watchdog timeout occurred */
CSL_WDT_WDFLAG_NOTIMEOUT = CSL_WDT_WDTCR_WDFLAG_NOTIMEOUT,
/** Watchdog timeout occurred */
CSL_WDT_WDFLAG_TIMEOUT = CSL_WDT_WDTCR_WDFLAG_TIMEOUT
}CSL_WdtFlagBitStatus;
/**
* @brief The enum describes the Enable Status of the watchdog timer.
*/
typedef enum{
/** watchdog disable */
CSL_WDT_WDEN_DISABLE = CSL_WDT_WDTCR_WDEN_DISABLE,
/** watchdog enable */
CSL_WDT_WDEN_ENABLE = CSL_WDT_WDTCR_WDEN_ENABLE
}CSL_WdtEnable;
/**
* @brief The enum describes the Idle State of the watchdog timer.
*/
typedef enum{
/** The sequence of a 01b followed
* by a 10b enable the watchdog to go in IDLE mode
*/
CSL_WDT_WDIKEY_IDLE_PRE_ENABLE = CSL_WDT_WDTCR_WDIKEY_GO_IDLE_START,
CSL_WDT_WDIKEY_IDLE_ENABLE = CSL_WDT_WDTCR_WDIKEY_GO_IDLE,
/** Disallow the watchdog timer goes into the IDLE mode */
CSL_WDT_WDIKEY_IDLE_DISABLE = CSL_WDT_WDTCR_WDIKEY_NO_IDLE
}CSL_WdtIdleSate;
/** @brief Structure toget the PID number
*/
typedef struct {
/** Identifies the type of peripheral */
Uint8 wdtType;
/** Identifies the class of peripheral */
Uint8 wdtClass;
/** Identifies the revision level of the timer */
Uint8 wdtRevision;
} CSL_WdtPidNumber;
/** @brief Hardware setup structure
*/
typedef struct {
/** 32 bit load value to be loaded to Timer Period Register 12 */
Uint32 wdtTimerPeriod12;
/** 32 bit load value to be loaded to Timer Period Register 34 */
Uint32 wdtTimerPeriod34;
/** Enabling mode, determines the enabling modes of the timer */
CSL_WdtTcr12Enamode wdtTcr12Enamode;
/** Pulse width, Only used in pulse mode by the timer controls
* the timer output.
*/
CSL_WdtTcr12PulseWidth wdtTcr12PulseWidth;
/** Configures the watchdog timer in watchdog mode or in
* general purpose timer mode or Dual 32 bit timer mode
*/
CSL_WdtTmrMode wdtTimerMode;
/** the timer functions properly in 64-bit timer mode both
* TIM34RS_ and TIM12RS_ must be set to '1'. Changing this bit
* does not affect the timer if the timer is in the watchdog
* active state.
*/
CSL_WdtTmr34State wdtTmr34State;
/** the timer functions properly in 64-bit timer mode both
* TIM34RS_ and TIM12RS_ must be set to '1'. Changing this bit
* does not affect the timer if the timer is in the watchdog
* active state.
*/
CSL_WdtTmr12State wdtTmr12State;
/** Watchdog flag bit, This bit can be cleared by enabling the watchdog
* timer, by device reset and by being written with '1'
*/
CSL_WdtFlagBitStatus wdtFlagBit;
} CSL_WdtHwSetup;
/**
* @brief Config-structure
*
* Used to configure the watchdog timer using CSL_wdtHwSetupRaw()
*/
typedef struct {
/** Emulation Management/Clock Speed registers setup raw*/
volatile Uint32 EMUMGT_CLKSPD;
/** General Purpose IO interrupt control and enable registers setup raw */
volatile Uint32 GPINT_GPEN;
/** General Purpose IO Data and Direction registers setup raw */
volatile Uint32 GPTDAT_GPDIR;
/** Timer Counter Register 12 setup raw */
volatile Uint32 TIM12;
/** Timer Counter Register 34 setup raw */
volatile Uint32 TIM34;
/** Timer Counter Register 12 setup raw */
volatile Uint32 PRD12;
/** Timer Counter Register 12 setup raw */
volatile Uint32 PRD34;
/** Timer Control Register setup raw */
volatile Uint32 TCR;
/** Timer Global Control Register setup raw */
volatile Uint32 TGCR;
/** Watchdog Timer Control Register setup raw */
volatile Uint32 WDTCR;
} CSL_WdtConfig;
/** @brief Module specific context information. Present implementation of watchdog
* timer CSL doesn't have any context information.
*/
typedef struct {
/** Context information of watchdog timer CSL.
* The below declaration is just a place-holder for future implementation.
*/
Uint16 contextInfo;
} CSL_WdtContext;
/** @brief Module specific parameters. Present implementation of watchdog timer CSL
* doesn't have any module specific parameters.
*/
typedef struct {
/** Bit mask to be used for module specific parameters. The below
* declaration is just a place-holder for future implementation.
*/
CSL_BitMask16 flags;
} CSL_WdtParam;
/** @brief This structure contains the base-address information for the peripheral
* instance
*/
typedef struct {
/** Base-address of the configuration registers of the peripheral
*/
CSL_WdtRegsOvly regs;
} CSL_WdtBaseAddress;
/** @brief Watchdog timer object structure
*/
typedef struct CSL_WdtObj {
/** Pointer to the register overlay structure of the watchdog timer */
CSL_WdtRegsOvly regs;
/** Instance of watchdog timer being referred by this object */
CSL_InstNum perNum;
} CSL_WdtObj;
/** @brief Default values for config structure
*/
#define CSL_WDT_CONFIG_DEFAULTS { \
CSL_WDT_EMUMGT_CLKSPD_RESETVAL, \
CSL_WDT_GPINT_GPEN_RESETVAL, \
CSL_WDT_GPTDAT_GPDIR_RESETVAL, \
CSL_WDT_TIM12_RESETVAL, \
CSL_WDT_TIM34_RESETVAL, \
CSL_WDT_PRD12_RESETVAL, \
CSL_WDT_PRD34_RESETVAL, \
CSL_WDT_TCR_RESETVAL, \
CSL_WDT_TGCR_RESETVAL, \
CSL_WDT_WDTCR_RESETVAL \
}
/** @brief Default hardware setup parameters
*/
#define CSL_WDT_HWSETUP_DEFAULTS { \
CSL_WDT_PRD12_RESETVAL, \
CSL_WDT_PRD34_RESETVAL, \
CSL_WDT_ENAMODE_CONTINU, \
CSL_WDT_PW_ONECLK, \
CSL_WDT_TIMMODE_WDT, \
CSL_WDT_TIM34RS_RESET, \
CSL_WDT_TIM12RS_RESET, \
CSL_WDT_WDFLAG_NOTIMEOUT \
}
/**
* @brief This data type is used to return the handle to the CSL of the watchdog
* timer
*/
typedef struct CSL_WdtObj *CSL_WdtHandle;
/*******************************************************************************
* Watchdog global function declarations
******************************************************************************/
/** ============================================================================
* @n@b CSL_wdtInit
*
* @b Description
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