csl_vlynq.h

TI达芬奇dm644x各硬件模块测试代码

    /** Serial Clock frequency is vlynq_clk_ref/(CSL_VLYNQ_CLKDIV_6 + 1) */
    CSL_VLYNQ_CLKDIV_6 = 6,

    /** Serial Clock frequency is vlynq_clk_ref/(CSL_VLYNQ_CLKDIV_7 + 1) */
    CSL_VLYNQ_CLKDIV_7 = 7

} CSL_VlynqSclkDiv;

/** @brief Enumeration for VLYNQ serial clock direction */
typedef enum {
    /** Clock sourced externally */
    CSL_VLYNQ_CLKDIR_EXTERNAL = 0, /*CSL_VLYNQ_CTRL_CLKDIR_INPUT */

    /** Internal clock source from divded down version of vlynq_clk_ref
     *  (VBUS Clock) */
    CSL_VLYNQ_CLKDIR_INTERNAL = 1 /*CSL_VLYNQ_CTRL_CLKDIR_OUTPUT*/
} CSL_VlynqClkDir;


/** @brief Enumeration for VLYNQ Interrpt type */
typedef enum {
    /** Level sensitive type */
    CSL_VLYNQ_INT_TYPELVL               = 0,

    /** Pulse tpye */
    CSL_VLYNQ_INT_TYPEPLS               = 1
} CSL_VlynqIntType;

/** @brief Enumeration for VLYNQ Interrpt polarity */
typedef enum {
    /** Active Low */
    CSL_VLYNQ_INT_POL_ACTIVE_LOW        = 0,

    /** Active High */
    CSL_VLYNQ_INT_POL_ACTIVE_HIGH       = 1
} CSL_VlynqIntPolType;

/** @brief Enumeration for VLYNQ Interrpt vector */
typedef enum {
    /** Interrupt Vector 0 */
    CSL_VLYNQ_INT_VECTOR_0              = 0,

    /** Interrupt Vector 1 */
    CSL_VLYNQ_INT_VECTOR_1              = 1,

    /** Interrupt Vector 2 */
    CSL_VLYNQ_INT_VECTOR_2              = 2,

    /** Interrupt Vector 3 */
    CSL_VLYNQ_INT_VECTOR_3              = 3,

    /** Interrupt Vector 4 */
    CSL_VLYNQ_INT_VECTOR_4              = 4,

    /** Interrupt Vector 5 */
    CSL_VLYNQ_INT_VECTOR_5              = 5,

    /** Interrupt Vector 6 */
    CSL_VLYNQ_INT_VECTOR_6              = 6,

    /** Interrupt Vector 7 */
    CSL_VLYNQ_INT_VECTOR_7              = 7,

    /** Interrupt Vector 8 */
    CSL_VLYNQ_INT_VECTOR_8              = 8,

    /** Interrupt Vector 9 */
    CSL_VLYNQ_INT_VECTOR_9              = 9,

    /** Interrupt Vector 10 */
    CSL_VLYNQ_INT_VECTOR_10             = 10,

    /** Interrupt Vector 11 */
    CSL_VLYNQ_INT_VECTOR_11             = 11,

    /** Interrupt Vector 12 */
    CSL_VLYNQ_INT_VECTOR_12             = 12,

    /** Interrupt Vector 13 */
    CSL_VLYNQ_INT_VECTOR_13             = 13,

    /** Interrupt Vector 14 */
    CSL_VLYNQ_INT_VECTOR_14             = 14,

    /** Interrupt Vector 15 */
    CSL_VLYNQ_INT_VECTOR_15             = 15,

    /** Interrupt Vector 16 */
    CSL_VLYNQ_INT_VECTOR_16             = 16,

    /** Interrupt Vector 17 */
    CSL_VLYNQ_INT_VECTOR_17             = 17,

    /** Interrupt Vector 18 */
    CSL_VLYNQ_INT_VECTOR_18             = 18,

    /** Interrupt Vector 19 */
    CSL_VLYNQ_INT_VECTOR_19             = 19,

    /** Interrupt Vector 20 */
    CSL_VLYNQ_INT_VECTOR_20             = 20,

    /** Interrupt Vector 21 */
    CSL_VLYNQ_INT_VECTOR_21             = 21,

    /** Interrupt Vector 22 */
    CSL_VLYNQ_INT_VECTOR_22             = 22,

    /** Interrupt Vector 23 */
    CSL_VLYNQ_INT_VECTOR_23             = 23,

    /** Interrupt Vector 24 */
    CSL_VLYNQ_INT_VECTOR_24             = 24,

    /** Interrupt Vector 25 */
    CSL_VLYNQ_INT_VECTOR_25             = 25,

    /** Interrupt Vector 26 */
    CSL_VLYNQ_INT_VECTOR_26             = 26,

    /** Interrupt Vector 27 */
    CSL_VLYNQ_INT_VECTOR_27             = 27,

    /** Interrupt Vector 28 */
    CSL_VLYNQ_INT_VECTOR_28             = 28,

    /** Interrupt Vector 29 */
    CSL_VLYNQ_INT_VECTOR_29             = 29,

    /** Interrupt Vector 30 */
    CSL_VLYNQ_INT_VECTOR_30             = 30,

    /** Interrupt Vector 31 */
    CSL_VLYNQ_INT_VECTOR_31             = 31
} CSL_VlynqIntVector;


/** @brief Enumeration for VLYNQ RTM Sample Values */
typedef enum {
    /** RTM Sample Value = 0 */
    CSL_VLYNQ_RXSAMPLEVAL_0             = 0,

    /** RTM Sample Value = 1 */
    CSL_VLYNQ_RXSAMPLEVAL_1             = 1,

    /** RTM Sample Value = 2 */
    CSL_VLYNQ_RXSAMPLEVAL_2             = 2,

    /** RTM Sample Value = 3 */
    CSL_VLYNQ_RXSAMPLEVAL_3             = 3,

    /** RTM Sample Value = 4 */
    CSL_VLYNQ_RXSAMPLEVAL_4             = 4,

    /** RTM Sample Value = 5 */
    CSL_VLYNQ_RXSAMPLEVAL_5             = 5,

    /** RTM Sample Value = 6 */
    CSL_VLYNQ_RXSAMPLEVAL_6             = 6,

    /** RTM Sample Value = 7 */
    CSL_VLYNQ_RXSAMPLEVAL_7             = 7
} CSL_VlynqRtmSampleVal;


/**
 * Module specific context information. Present implementation of VLYNQ
 * CSL doesn't have any context information.
 */
typedef struct {
    /**
     * Context information of VLYNQ port CSL.
     * The below declaration is just a place-holder for future implementation.
     */
    Uint16  contextInfo;
} CSL_VlynqContext;

/**
 * Module specific parameters. Present implementation of VLYNQ CSL
 * doesn't have any module specific parameters.
 */
typedef struct {
    /**
     * Bit mask to be used for module specific parameters. The below
     * declaration is just a place-holder for future implementation.
     */
    CSL_BitMask16       flags;
} CSL_VlynqParam;

/**
 * This structure contains the base-address information for the peripheral
 * instance.
 */
typedef struct {
    /** Base-address of the configuration registers of the peripheral */
    CSL_VlynqRegsOvly       regs;
} CSL_VlynqBaseAddress;

/** @brief this object contains the reference to the instance of VLYNQ
 * opened using the @a CSL_vlynqOpen()
 *
 * The pointer to this is passed to all VLYNQ CSL APIs. */
typedef struct CSL_VlynqObj {
    /** This is a pointer to the registers of the instance of VLYNQ
     * referred to by this object */
    CSL_VlynqRegsOvly    regs;

    /** This is the instance of VLYNQ being referred to by this object */
    CSL_InstNum         perNum;
} CSL_VlynqObj;

/** @brief this is a pointer to @a CSL_VlynqObj & is passed as the first
 * parameter to all VLYNQ CSL APIs */
typedef struct CSL_VlynqObj *CSL_VlynqHandle;

/** @brief this is a void pointer used to point register, memory-location */
typedef void *CSL_VlynqAdrPtr;


/** @brief main structure that is used to setup the VLYNQ's control reg
 *
 * This structure is used to setup or obtain the existing setup of
 * VLYNQ using @a CSL_vlynqHwSetup() & @a CSL_vlynqGetHwStatus() functions
 * respectively. If a particualr member pointer is null, then these
 * functions do not setup or get the setup of the corresponding part
 * of VLYNQ respectively */
typedef struct CSL_VlynqHwControlSetup {
    /** Power Management Enable */
    Bool                    pMen;

    /** Serial Clock pull-up Disable*/
    Bool                    sclkPuDis;

    /** RTM Sample Value (Defualt = 0x03)*/
    CSL_VlynqRtmSampleVal   rxSampleVal;

    /** RTM Valid Write (0-write is invalid for rxsampleval) */
    Bool                    rtmValidWr;

    /** RTM Enable (0-Disable) */
    Bool                    rtmEnable;

    /** TX transmit Path (0-Slow) */
    Bool                    txFastPath;

    /** Serial Clock Divider for VLYNQ */
    CSL_VlynqSclkDiv        sclkDiv;

    /** Clock direction */
    CSL_VlynqClkDir         sclkDir;

    /** Interrupt Post (1-local INTSTATCLR reg)
     *  (0-packet transmission via setial interface) */
    Bool                    intLocal;

    /** VLYNQ Status interrupts enable/disable (0-Disable) */
    Bool                    intEnable;

    /** Interrupt to Configuration Register
     *  (1-Interrupt packet is written to local config register)
     *  (0-Interrupt packet is written to memory pointed by INTPTR reg) */
    Bool                    int2cfg;

    /** Address Optimization Disable (1-Disable) */
    Bool                    aOptDisable;

    /** Internal Loopback (0-Disable) */
    Bool                    iLoop;

    /** Soft reset (0-Reset Deassert) */
    Bool                    reset;

    /** Interrupt Pointer (default pointer to INTPENDSET-offset 0x14) */
    CSL_VlynqAdrPtr         intPtr;

    /** Tx Address Map */
    CSL_VlynqAdrPtr         txAdrMap;

    /** Rx Addres Map Size1 */
    Uint32                  rxAdrSize1;

    /** Rx Address Map Offset1 */
    CSL_VlynqAdrPtr         rxAdrOffset1;

    /** Rx Addres Map Size2 */
    Uint32                  rxAdrSize2;

    /** Rx Address Map Offset2 */
    CSL_VlynqAdrPtr         rxAdrOffset2;

    /** Rx Addres Map Size3 */
    Uint32                  rxAdrSize3;

    /** Rx Address Map Offset3 */
    CSL_VlynqAdrPtr         rxAdrOffset3;

    /** Rx Addres Map Size4 */
    Uint32                  rxAdrSize4;

    /** Rx Address Map Offset4 */
    CSL_VlynqAdrPtr         rxAdrOffset4;
} CSL_VlynqHwControlSetup;


/** @brief this is a pointer to @a CSL_VlynqHwControlSetup &
 *  is passed as parameter to all VLYNQ CSL APIs */
typedef CSL_VlynqHwControlSetup *CSL_VlynqPtrHwSetup;


/** @brief main structure that is used to setup the VLYNQ module
 *
 * This structure is used to setup or obtain the existing setup of
 * VLYNQ using @a CSL_vlynqHwSetup() & @a CSL_vlynqGetHwStatus() functions
 * respectively. If a particualr member pointer is null, then these
 * functions do not setup or get the setup of the corresponding part
 * of VLYNQ respectively */
typedef struct CSL_VlynqHwSetup {
    /** Pointer to CSL_VlynqHwControlSetup used to hold the
     *  information for local VLYNQ's control setup */
    CSL_VlynqPtrHwSetup     localHwSetup;

    /** Pointer to CSL_VlynqHwControlSetup used to hold the
     *  information for remote VLYNQ's control setup */
    CSL_VlynqPtrHwSetup     remoteHwSetup;
} CSL_VlynqHwSetup;


/** Config structure of NAND. This is used to configure NAND
 * using CSL_HwSetupRaw function
 */
typedef struct  {
    /** Control Register  */
    volatile Uint32 CTRL;
    /** Interrupt Priority Vector Status/Clear Register */
    volatile Uint32 INTPRI;
    /** Interrupt status/clear register */
    volatile Uint32 INTSTATCLR;
    /** Interrupt Pending/Set Register */
    volatile Uint32 INTPENDSET;
    /** Interrupt Pointer Register */
    volatile Uint32 INTPTR;
    /** Tx Address Map Register */
    volatile Uint32 XAM;
    /** Rx Address Map Size 1 Register */
    volatile Uint32 RAMS1;
    /** Rx Address Map Offset 1 Register */
    volatile Uint32 RAMO1;
    /** Rx Address Map Size 2 Register */
    volatile Uint32 RAMS2;
    /** Rx Address Map Offset 2 Register */
    volatile Uint32 RAMO2;
    /** Rx Address Map Size 3 Register */
    volatile Uint32 RAMS3;
    /** Rx Address Map Offset 3 Register */
    volatile Uint32 RAMO3;
    /** Rx Address Map Size 4 Register */
    volatile Uint32 RAMS4;
    /** Rx Address Map Offset 4 Register */
    volatile Uint32 RAMO4;
    /** Interrupt Vector 3-0 Register */
    volatile Uint32 INTVEC0;
    /** Interrupt Vector 7-4 Register */
    volatile Uint32 INTVEC1;
    /** Remote Control Register */
    volatile Uint32 RCTRL;
    /** Remote Interrupt Priority Vector Status/Clear Register */
    volatile Uint32 RINTPRI;
    /** Remote Status Register */
    volatile Uint32 RINTSTATCLR;
    /** Remote Interrupt Pending/Set Register */
    volatile Uint32 RINTPENDSET;
    /** Remote Interrupt Pointer Register */
    volatile Uint32 RINTPTR;
    /** Remote Tx Address Map Register */
    volatile Uint32 RXAM;
    /** Remote Rx Address Map Size 1 Register */
    volatile Uint32 RRAMS1;
    /** Remote Rx Address Map Offset 1 Register */
    volatile Uint32 RRAMO1;
    /** Remote Rx Address Map Size 2 Register */
    volatile Uint32 RRAMS2;
    /** Remote Rx Address Map Offset 2 Register */
    volatile Uint32 RRAMO2;
    /** Remote Rx Address Map Size 3 Register */
    volatile Uint32 RRAMS3;
    /** Remote Rx Address Map Offset 3 Register */
    volatile Uint32 RRAMO3;
    /** Remote Rx Address Map Size 4 Register */
    volatile Uint32 RRAMS4;
    /** Remote Rx Address Map Offset 4 Register */
    volatile Uint32 RRAMO4;
    /** Remote Interrupt Vector 3-0 Register */
    volatile Uint32 RINTVEC0;
    /** Remote Interrupt Vector 7-4 Register */
    volatile Uint32 RINTVEC1;
} CSL_VlynqConfig;