csl_vlynq.h

TI达芬奇dm644x各硬件模块测试代码

    /** Assert remote VLYNQ's Soft RESET */
    CSL_VLYNQ_CMD_REMOTE_SOFTRESET_ASSERT = 101,

    /** Clear remote error status flag at remote VLYNQ */
    CSL_VLYNQ_CMD_REMOTE_RERROR_CLR     = 102,
    /** Clear local error status flag at remote VLYNQ */
    CSL_VLYNQ_CMD_REMOTE_LERROR_CLR     = 103,

    /** Clear remote VLYNQ's interrupt status (which has got highest
     *  priority) pending from the RINTSTATCLR register */
    CSL_VLYNQ_CMD_REMOTE_INTPRI_INTSTAT_CLR = 104,

    /** Clear remote VLYNQ's interrupt(s) status bits
     *  (refers to RINTSTATCLR) */
    CSL_VLYNQ_CMD_REMOTE_INTSTATCLR_INTCLR_CLR = 105,

    /** Sets/generates remote VLYNQ's interrupt
     *  (refers to RINTPENDSET register) */
    CSL_VLYNQ_CMD_REMOTE_INTPENDSET_INTSET_SET = 106,
    /** Clear remote VLYNQ's pending interrupts from RINTPENDSET register */
    CSL_VLYNQ_CMD_REMOTE_INTPENDSET_INTSET_CLR = 107,

    /** Sets remote VLYNQ's RINTPTR to point a configuration register */
    CSL_VLYNQ_CMD_REMOTE_INTPTR_REGPTR  = 108,
    /** Sets remote VLYNQ's RINTPTR to point to memory */
    CSL_VLYNQ_CMD_REMOTE_INTPTR_MEMPTR  = 109,

    /** Sets remote VLYNQ's  Tx Address Map (RXAM) register with a given
     *  address/value used in translating the transmit packet address */
    CSL_VLYNQ_CMD_REMOTE_XAM_TXADRMAP_SET = 110,

    /** Sets remote VLYNQ's Rx Address Map Size1 (RRAMS1) register with
     *  a given address/value used in calculating the inbound packet
     *  address */
    CSL_VLYNQ_CMD_REMOTE_RAMS1_RXADRSIZE1_SET    = 111,
    /** Sets remote VLYNQ's Rx Address Map Offset1 (RRAMO1) register with
     *  a given address/value used in calculating the inbound
     *  packet address */
    CSL_VLYNQ_CMD_REMOTE_RAMO1_RXADROFFSET1_SET  = 112,

    /** Sets remote VLYNQ's Rx Address Map Size2 (RRAMS2) register with
     *  a given address/value used in calculating the inbound
     *  packet address */
    CSL_VLYNQ_CMD_REMOTE_RAMS2_RXADRSIZE2_SET    = 113,
    /** Sets remote VLYNQ's Rx Address Map Offset2 (RRAMO2) register with
     *  a given address/value used in calculating the inbound
     *  packet address */
    CSL_VLYNQ_CMD_REMOTE_RAMO2_RXADROFFSET2_SET  = 114,

    /** Sets remote VLYNQ's Rx Address Map Size3 (RRAMS3) register with
     *  a given address/value used in calculating the inbound
     *  packet address */
    CSL_VLYNQ_CMD_REMOTE_RAMS3_RXADRSIZE3_SET    = 115,
    /** Sets remote VLYNQ's Rx Address Map Offset3 (RRAMO3) register with
     *  a given address/value used in calculating the inbound
     *  packet address */
    CSL_VLYNQ_CMD_REMOTE_RAMO3_RXADROFFSET3_SET  = 116,

    /** Sets remote VLYNQ's Rx Address Map Size4 (RRAMS4) register with
     *  a given address/value used in calculating the inbound
     *  packet address */
    CSL_VLYNQ_CMD_REMOTE_RAMS4_RXADRSIZE4_SET    = 117,
    /** Sets remote VLYNQ's Rx Address Map Offset4 (RRAMO4) register with
     *  a given address/value used in calculating the inbound
     *  packet address */
    CSL_VLYNQ_CMD_REMOTE_RAMO4_RXADROFFSET4_SET  = 118,

    /** Enable remote VLYNQ's RINTVEC0 (3-0) interrupt(s) */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT_ENA         = 119,
    /** Disable remote VLYNQ's RINTVEC0 (3-0) interrupt(s) */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT_DIS         = 120,

    /** RINTVEC0s' (remote VLYNQ's) Interrupt-3 type */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT3_TYPE_SET   = 121,
    /** RINTVEC0s' (remote VLYNQ's) Interrupt-3 polarity */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT3_POL_SET    = 122,
    /** RINTVEC0's (remote VLYNQ's) Interrupt-3 interrupt vector */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT3_INTVEC_SET = 123,

    /** RINTVEC0s' (remote VLYNQ's) Interrupt-2 type */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT2_TYPE_SET   = 124,
    /** RINTVEC0s' (remote VLYNQ's) Interrupt-2 polarity */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT2_POL_SET    = 125,
    /** RINTVEC0's (remote VLYNQ's) Interrupt-2 interrupt vector */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT2_INTVEC_SET = 126,

    /** RINTVEC0s' (remote VLYNQ's) Interrupt-1 type */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT1_TYPE_SET   = 127,
    /** RINTVEC0s' (remote VLYNQ's) Interrupt-1 polarity */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT1_POL_SET    = 128,
    /** RINTVEC0's (remote VLYNQ's) Interrupt-1 interrupt vector */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT1_INTVEC_SET = 129,

    /** RINTVEC0s' (remote VLYNQ's) Interrupt-0 type */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT0_TYPE_SET   = 130,
    /** RINTVEC0s' (remote VLYNQ's) Interrupt-0 polarity */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT0_POL_SET    = 131,
    /** RINTVEC0's (remote VLYNQ's) Interrupt-0 interrupt vector */
    CSL_VLYNQ_CMD_REMOTE_INTVEC0_INT0_INTVEC_SET = 132,


    /** Enable remote VLYNQ's RINTVEC1 (7-4) interrupt(s) */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT_ENA         = 133,
    /** Disable remote VLYNQ's RINTVEC1 (7-4) interrupt(s) */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT_DIS         = 134,

    /** RINTVEC1s' (remote VLYNQ's) Interrupt-7 type */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT7_TYPE_SET   = 135,
    /** RINTVEC1s' (remote VLYNQ's) Interrupt-7 polarity */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT7_POL_SET    = 136,
    /** RINTVEC1's (remote VLYNQ's) Interrupt-7 interrupt vector */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT7_INTVEC_SET = 137,

    /** RINTVEC1s' (remote VLYNQ's) Interrupt-6 type */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT6_TYPE_SET   = 138,
    /** RINTVEC1s' (remote VLYNQ's) Interrupt-6 polarity */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT6_POL_SET    = 139,
    /** RINTVEC1's (remote VLYNQ's) Interrupt-6 interrupt vector */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT6_INTVEC_SET = 140,

    /** RINTVEC1s' (remote VLYNQ's) Interrupt-5 type */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT5_TYPE_SET   = 141,
    /** RINTVEC1s' (remote VLYNQ's) Interrupt-5 polarity */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT5_POL_SET    = 142,
    /** RINTVEC1's (remote VLYNQ's) Interrupt-5 interrupt vector */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT5_INTVEC_SET = 143,

    /** RINTVEC1s' (remote VLYNQ's) Interrupt-4 type */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT4_TYPE_SET   = 144,
    /** RINTVEC1s' (remote VLYNQ's) Interrupt-4 polarity */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT4_POL_SET    = 145,
    /** RINTVEC1's (remote VLYNQ's) Interrupt-4 interrupt vector */
    CSL_VLYNQ_CMD_REMOTE_INTVEC1_INT4_INTVEC_SET = 146

} CSL_VlynqHwControlCmd;


/** @brief Enumeration for queries passed to @a CSL_vlynqGetHwStatus()
 *
 * This is used to get the status of different operations or to get the
 * existing setup of VLYNQ. The arguments to be passed with each
 * enumeration if any are specified next to the enumeration */
typedef enum {
/** Queries related to local VLYNQ */
    /** unique ID of VLYNQ module */
    CSL_VLYNQ_QUERY_REVID               = 1,

    /*Razak: added following 2 queries for major & minor revisions */
    /** major revision of VLYNQ module */
    CSL_VLYNQ_QUERY_REVMAJ              = 2,

    /** minor revision of VLYNQ module */
    CSL_VLYNQ_QUERY_REVMIN              = 3,

    /** Power Management info */
    CSL_VLYNQ_QUERY_PMEN                = 4,

    /* Razak: added following query */
    /** value in rxsmapleval bit-field */
    CSL_VLYNQ_QUERY_RXSAMPLEVAL         = 5,

    /** RTM Logic info */
    CSL_VLYNQ_QUERY_RTMENABLE           = 6,

    /** Transmit Path */
    CSL_VLYNQ_QUERY_TXFASTPATH          = 7,

    /** Serial clock direction */
    CSL_VLYNQ_QUERY_CLKDIR              = 8,

    /** Interrupt Postage Info (local/serial interface) */
    CSL_VLYNQ_QUERY_INTLOCAL            = 9,

    /** Status Interrupts Enanbled/Disabled */
    CSL_VLYNQ_QUERY_INTENABLE           = 10,

    /** intvec: Interrupts Vector Status
     *  (bit in INTPENDSET, set for VLYNQ module) */
    CSL_VLYNQ_QUERY_INTVEC              = 11,

    /** INT2CFG Status: writing the status of Interrupt Packet
     *  to (Config-reg or memory) */
    CSL_VLYNQ_QUERY_INT2CFG             = 12,

    /** Address Optimization */
    CSL_VLYNQ_QUERY_AOPTDISABLE         = 13,

    /** Internal Loop */
    CSL_VLYNQ_QUERY_ILOOP               = 14,

    /** Size/Width of inbound serial data */
    CSL_VLYNQ_QUERY_SWIDTHIN            = 15,

    /** Size/Width of outbound serial data */
    CSL_VLYNQ_QUERY_SWIDTHOUT           = 16,

    /** Current clock sample value used by RTM */
    CSL_VLYNQ_QUERY_RXCURRENTSAMPLE     = 17,

    /** RTM logic inclusion in RTL */
    CSL_VLYNQ_QUERY_RTM                 = 18,

    /** Inbound Flow Control */
    CSL_VLYNQ_QUERY_IFLOW               = 19,

    /** Outbound Flow Control */
    CSL_VLYNQ_QUERY_OFLOW               = 20,

    /** Remote Packet Error status */
    CSL_VLYNQ_QUERY_RERROR              = 21,

    /** Local/ Inbound Packet Error status */
    CSL_VLYNQ_QUERY_LERROR              = 22,

    /** FIFO-3 Slave Command FIFO not empty status */
    CSL_VLYNQ_QUERY_NFEMPTY3            = 23,

    /** FIFO-2 Slave Data FIFO not empty status */
    CSL_VLYNQ_QUERY_NFEMPTY2            = 24,

    /** FIFO-1 Master Command FIFO not empty status */
    CSL_VLYNQ_QUERY_NFEMPTY1            = 25,

    /** FIFO-0 Master Data FIFO not empty status */
    CSL_VLYNQ_QUERY_NFEMPTY0            = 26,

    /** Any Pending Requests at Slave Interface */
    CSL_VLYNQ_QUERY_SPEND               = 27,

    /** Any Pending Requests at Master Interface */
    CSL_VLYNQ_QUERY_MPEND               = 28,

    /** Status of Serial Link establishment */
    CSL_VLYNQ_QUERY_LINK                = 29,

    /** Any pending interrupts from INTSTATCLR register */
    CSL_VLYNQ_QUERY_INTPRI_NOINTPEND    = 30,

    /** Status of the highest priority interrupt pending from
     *  INTSTATCLR register */
    CSL_VLYNQ_QUERY_INTPRI_INTSTAT      = 31,

    /** Status flags of interrupt(s) from INTSTATCLR register */
    CSL_VLYNQ_QUERY_INTSTATCLR_INTCLR   = 32,

    /** Status of interrupt/s pending from INTPENDSET register */
    CSL_VLYNQ_QUERY_INTPENDSET_INTSET   = 33,

    /** Get address of Config-reg/mem-location from INTPTR */
    CSL_VLYNQ_QUERY_INTPTR              = 34,

    /** Get Chip version (Type and Version of VLYNQ device) */
    CSL_VLYNQ_QUERY_CHIPVER             = 35,

    /** Get the Auto Negotiation Protocol Info (2.x or 1.x) */
    CSL_VLYNQ_QUERY_AUTONGO_2X          = 36,

/** Queries related to remote VLYNQ */

    /** major and minor revision of remote VLYNQ module */
    CSL_VLYNQ_QUERY_REMOTE_REVID        = 37,

    /*Razak: added following 2 queries for major & minor revisions */
    /** major revision of remote VLYNQ module */
    CSL_VLYNQ_QUERY_REMOTE_REVMAJ       = 38,

    /** minor revision of VLYNQ module */
    CSL_VLYNQ_QUERY_REMOTE_REVMIN       = 39,

    /** Power Management info of remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_PMEN         = 40,

    /* Razak: added following query */
    /** value in rxsmapleval bit-field of remote VLYNQ*/
    CSL_VLYNQ_QUERY_REMOTE_RXSAMPLEVAL  = 41,

    /** RTM Logic info of remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_RTMENABLE    = 42,

    /** Transmit Path of remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_TXFASTPATH   = 43,

    /** Serial clock direction of remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_CLKDIR       = 44,

    /** Remote VLYNQs' Interrupt Postage Info (local/serial interface) */
    CSL_VLYNQ_QUERY_REMOTE_INTLOCAL     = 45,

    /** Remote VLYNQs' Status Interrupts Enanbled/Disabled */
    CSL_VLYNQ_QUERY_REMOTE_INTENABLE    = 46,

    /** Remote VLYNQs'intvec: Interrupts Vector Status
     *  (bit in INTPENDSET, set for VLYNQ module) */
    CSL_VLYNQ_QUERY_REMOTE_INTVEC       = 47,

    /** Remote VLYNQs' INT2CFG Status: writing the status of Interrupt Packet
     *  to (Config-reg or memory) */
    CSL_VLYNQ_QUERY_REMOTE_INT2CFG      = 48,

    /** Address Optimization of remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_AOPTDISABLE  = 49,

    /** Internal Loop info of remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_ILOOP        = 50,

    /** Remote VLYNQs' Size/Width of inbound serial data */
    CSL_VLYNQ_QUERY_REMOTE_SWIDTHIN     = 51,

    /** Remote VLYNQs' Size/Width of outbound serial data */
    CSL_VLYNQ_QUERY_REMOTE_SWIDTHOUT    = 52,

    /** Current clock sample value used by RTM at remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_RXCURRENTSAMPLE = 53,

    /** Remote VLYNQs' RTM logic inclusion in RTL */
    CSL_VLYNQ_QUERY_REMOTE_RTM          = 54,

    /** Remote VLYNQs' inbound Flow Control */
    CSL_VLYNQ_QUERY_REMOTE_IFLOW        = 55,

    /** Remote VLYNQs' outbound Flow Control */
    CSL_VLYNQ_QUERY_REMOTE_OFLOW        = 56,

    /** Remote Packet Error status of remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_RERROR       = 57,

    /** Local/Inbound Packet Error status of remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_LERROR       = 58,

    /** Remote VLYNQs' FIFO-3 Slave Command FIFO not empty status */
    CSL_VLYNQ_QUERY_REMOTE_NFEMPTY3     = 59,

    /** Remote VLYNQs' FIFO-2 Slave Data FIFO not empty status */
    CSL_VLYNQ_QUERY_REMOTE_NFEMPTY2     = 60,

    /** Remote VLYNQs' FIFO-1 Master Command FIFO not empty status */
    CSL_VLYNQ_QUERY_REMOTE_NFEMPTY1     = 61,

    /** Remote VLYNQs' FIFO-0 Master Data FIFO not empty status */
    CSL_VLYNQ_QUERY_REMOTE_NFEMPTY0     = 62,

    /** Any Pending Requests at Slave Interface in remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_SPEND        = 63,

    /** Any Pending Requests at Master Interface in remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_MPEND        = 64,

    /** Serial Link establishment status of remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_LINK         = 65,

    /** Any pending interrupts in INTSTATCLR register in remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_INTPRI_NOINTPEND = 66,

    /** Status of the highest priority interrupt pending from
     *  INTSTATCLR register in remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_INTPRI_INTSTAT = 67,

    /** Status flags of interrupt(s) in INTSTATCLR register
     *  in remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_INTSTATCLR_INTCLR = 68,

    /** Status of interrupt(s) pending from INTPENDSET register
     *  in remote VLYNQ */
    CSL_VLYNQ_QUERY_REMOTE_INTPENDSET_INTSET = 69,

    /** Get address of Config-reg/mem-location from INTPTR of remote VLYNQ*/
    CSL_VLYNQ_QUERY_REMOTE_INTPTR       = 70,

    /** Get remote VLYNQs'Chip version (Type and Version of VLYNQ device) */
    CSL_VLYNQ_QUERY_REMOTE_CHIPVER      = 71,

    /** Get remote VLYNQs' Auto Negotiation Protocol Info (2.x or 1.x) */
    CSL_VLYNQ_QUERY_REMOTE_AUTONGO_2X   = 72

} CSL_VlynqHwStatusQuery;


/** @brief Enumeration for VLYNQ serial clock output divider */
typedef enum {
    /** Serial Clock frequency is vlynq_clk_ref/(CSL_VLYNQ_CLKDIV_0 + 1) */
    CSL_VLYNQ_CLKDIV_0 = 0,

    /** Serial Clock frequency is vlynq_clk_ref/(CSL_VLYNQ_CLKDIV_1 + 1) */
    CSL_VLYNQ_CLKDIV_1 = 1,

    /** Serial Clock frequency is vlynq_clk_ref/(CSL_VLYNQ_CLKDIV_2 + 1) */
    CSL_VLYNQ_CLKDIV_2 = 2,

    /** Serial Clock frequency is vlynq_clk_ref/(CSL_VLYNQ_CLKDIV_3 + 1) */
    CSL_VLYNQ_CLKDIV_3 = 3,

    /** Serial Clock frequency is vlynq_clk_ref/(CSL_VLYNQ_CLKDIV_4 + 1) */
    CSL_VLYNQ_CLKDIV_4 = 4,

    /** Serial Clock frequency is vlynq_clk_ref/(CSL_VLYNQ_CLKDIV_5 + 1) */
    CSL_VLYNQ_CLKDIV_5 = 5,