csl_vlynq.h

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/** @file csl_vlynq.h
 *
 *  @brief  Header file for functional layer of VLYNQ CSL
 *
 *  Description
 *  - Comprises the function declarations for the various APIs and the
 *    associated enumerations, type and symbol definitions for the VLYNQ
 *    module.
 *
 *  Path: \\(CSLPATH)\\ipmodules\\vlynq\\src
 */

/** @mainpage VLYNQ CSL 3.x
 *
 *  @section Introduction
 *
 *  @subsection xxx Purpose and Scope
 *  The purpose of this document is to identify a set of common CSL APIs for
 *  the VLYNQ module across various devices. The CSL developer is expected to
 *  refer to this document while designing APIs for these modules. Some of the
 *  listed APIs may not be applicable to a given VLYNQ module. While other cases
 *  this list of APIs may not be sufficient to cover all the features of a
 *  particular VLYNQ Module. The CSL developer should use his discretion
 *  designing new APIs or extending the existing ones to cover these.
 *
 *  @subsection aaa Terms and Abbreviations
 *    -# CSL:  Chip Support Library
 *    -# API:  Application Programmer Interface
 *
 *  @subsection References
 *     -# CSL-001-DES, CSL 3.x Design Specification Document Version 1.02
 */

/* =============================================================================
 *  Revision History
 *  ===============
 *  17-Dec-04 Nsr updated CSL_VlynqObj and added CSL_VlynqBaseAddress,
 *                CSL_vlynqParam, CSL_vlynqContext, CSL_vlynqConfig structures.
 *                Updated comments for H/W control cmd and status query enums.
 *                Added prototypes for CSL_vlynqGetBaseAdddress and
 *                CSL_VlynqHwSetupRaw.
 *                Changed prototypes of CSL_vlynqInit, CSL_vlynqOpen.
 *                Updated respective comments along with that of CSL_vlynqClose.
 * =============================================================================
 */

#ifndef _CSL_VLYNQ_H_
#define _CSL_VLYNQ_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>
#include <csl_error.h>
#include <csl_types.h>
#include <cslr_vlynq.h>
#include <soc.h>

/**************************************************************************\
* VLYNQ global macro declarations
\**************************************************************************/

#define     CSL_VLYNQ_PER_ANY                   -1

#define     CSL_VLYNQ_INTPTR_DEF_VAL            0x14

#define     CSL_VLYNQ_DEFAULT_RXSAMPLEVAL       0x03

#define     CSL_VLYNQ_STAT_RERROR_CLEAR         0x01
#define     CSL_VLYNQ_STAT_LERROR_CLEAR         0x01
/** Enable interrupts for VLYNQ  */
#define     CSL_VLYNQ_INT_ENA                   0x01
/** Disable interrupts for VLYNQ  */
#define     CSL_VLYNQ_INT_DIS                   0x00
#define     CSL_VLYNQ_INT_TYPE_PLS              0x01
#define     CSL_VLYNQ_INT_TYPE_LVL              0x00
#define     CSL_VLYNQ_INT_POL_ACTIVELOW         0x01
#define     CSL_VLYNQ_INT_POL_ACTIVEHIGH        0x00
/** INTVEC0's Interrupt3 */
#define     CSL_VLYNQ_INTVEC0_INT3              0x80000000
/** INTVEC0's Interrupt2 */
#define     CSL_VLYNQ_INTVEC0_INT2              0x00800000
/** INTVEC0's Interrupt1 */
#define     CSL_VLYNQ_INTVEC0_INT1              0x00008000
/** INTVEC0's Interrupt0 */
#define     CSL_VLYNQ_INTVEC0_INT0              0x00000080
/** INTVEC1's Interrupt7 */
#define     CSL_VLYNQ_INTVEC0_INT7              0x80000000
/** INTVEC1's Interrupt6 */
#define     CSL_VLYNQ_INTVEC0_INT6              0x00800000
/** INTVEC1's Interrupt5 */
#define     CSL_VLYNQ_INTVEC0_INT5              0x00008000
/** INTVEC1's Interrupt4 */
#define     CSL_VLYNQ_INTVEC0_INT4              0x00000080

/**************************************************************************\
* VLYNQ global typedef declarations
\**************************************************************************/

#if 0
/** @brief Enumeration for VLYNQ instances
 *
 * This is the serial number of VLYNQ as reflected in the device specifications.
 * There is only one instance of VLYNQ in the device */
typedef enum {
    CSL_VLYNQ_0  =  0
} CSL_VlynqNum;
#endif


/** @brief Enumeration for control commands passed to @a CSL_vlynqHwControl()
 *
 * This is the set of commands that are passed to the @a CSL_vlynqHwControl()
 * with an optional argument type-casted to @a void* . The arguments to be
 * passed with each enumeration if any are specified next to the enumeration*/
typedef enum {
/** Commands for local VLYNQs' configuration register */
    /** Enable Power Management */
    CSL_VLYNQ_CMD_PMEN_ENA              = 1,
    /** Disable Power Management */
    CSL_VLYNQ_CMD_PMEN_DIS              = 2,

    /** Serial Clock Pull-up Disable */
    CSL_VLYNQ_CMD_SCLKPUDIS_DIS         = 3,
    /** Serial Clock Pull-up Enable */
    CSL_VLYNQ_CMD_SCLKPUDIS_ENA         = 4,

    /** Set RTM sample value */
    CSL_VLYNQ_CMD_RXSAMPLEVAL_SET       = 5,

    /** Disable the RTM Write valid (rxsample val will be invalid) */
    CSL_VLYNQ_CMD_RTMVALIDWR_DIS        = 6,
    /** Enable RTM Write valid */
    CSL_VLYNQ_CMD_RTMVALIDWR_ENA        = 7,

    /** Disable RTM (Receive Timing Manager) */
    CSL_VLYNQ_CMD_RTMENABLE_DIS         = 8,
    /** Enable RTM (Receive Timing Manager) */
    CSL_VLYNQ_CMD_RTMENABLE_ENA         = 9,

    /** Selects TX Slow path */
    CSL_VLYNQ_CMD_TXFASTPATH_DIS        = 10,
    /** Selects TX fast path */
    CSL_VLYNQ_CMD_TXFASTPATH_ENA        = 11,

    /** Selects Serial Clock divider value */
    CSL_VLYNQ_CMD_CLKDIV_SET            = 12,

    /** VLYNQ uses internal clock, divided down vesrion of vlynk_clk_ref */
    CSL_VLYNQ_CMD_CLKDIR_OUTPUT         = 13,
    /** VLYNQ clock is sourced externally */
    CSL_VLYNQ_CMD_CLKDIR_INPUT          = 14,

    /** Post Interrupts locally */
    CSL_VLYNQ_CMD_INTLOCAL_LOCAL        = 15,
    /** Forward/Transmit Interrupt packets over serial- interface */
    CSL_VLYNQ_CMD_INTLOCAL_REMOTE       = 16,

    /** Enables Status Interrupts */
    CSL_VLYNQ_CMD_INTENABLE_ENA         = 17,
    /** Disables Status Interrupts */
    CSL_VLYNQ_CMD_INTENABLE_DIS         = 18,

    /*Razak: Added following 2 new command for writing to 'intvec'
     *  field of CTRL reg */
    /** Sets intvec field */
    CSL_VLYNQ_CMD_INTVEC_SET            = 19,
    /** Clears intvec field */
    CSL_VLYNQ_CMD_INTVEC_CLR            = 20,

    /** Use INTPTR register as a pointer to Configuration
     *  register */
    CSL_VLYNQ_CMD_INT2CFG_ENA           = 21,
    /** Use INTPTR register as a pointer to memory */
    CSL_VLYNQ_CMD_INT2CFG_DIS           = 22,

    /** Disable Address Optimization */
    CSL_VLYNQ_CMD_AOPTDISABLE_DIS       = 23,
    /** Enable Address Optimization */
    CSL_VLYNQ_CMD_AOPTDISABLE_ENA       = 24,

    /** Enable internal loop-back */
    CSL_VLYNQ_CMD_ILOOP_ENA             = 25,
    /** Disable internal loop-back */
    CSL_VLYNQ_CMD_ILOOP_DIS             = 26,

    /** Assert soft reset */
    CSL_VLYNQ_CMD_SOFTRESET_ASSERT      = 27,
    /** Deassert soft reset */
    CSL_VLYNQ_CMD_SOFTRESET_DEASSERT    = 28,

    /** Clear remote error status flag */
    CSL_VLYNQ_CMD_RERROR_CLR            = 29,
    /** Clear local error status flag */
    CSL_VLYNQ_CMD_LERROR_CLR            = 30,

    /** Clears the interrupt status (which has got highest priority)
     *  pending from the INTSTATCLR register */
    CSL_VLYNQ_CMD_INTPRI_INTSTAT_CLR    = 31,

    /** Clear interrupt(s) status bits (refers to INTSTATCLR) */
    CSL_VLYNQ_CMD_INTSTATCLR_INTCLR_CLR = 32,

    /** Sets/generates interrupt (refers to INTPENDSET register) */
    CSL_VLYNQ_CMD_INTPENDSET_INTSET_SET = 33,
    /** Clear pending interrupts from INTPENDSET register */
    CSL_VLYNQ_CMD_INTPENDSET_INTSET_CLR = 34,

    /** Sets the INTPTR to point a configuration register */
    CSL_VLYNQ_CMD_INTPTR_REGPTR         = 35,
    /** Sets the INTPTR to point to memory */
    CSL_VLYNQ_CMD_INTPTR_MEMPTR         = 36,

    /** Sets the Tx Address Map (XAM) register with a given address/value
     *  used in translating the transmit packet address */
    CSL_VLYNQ_CMD_XAM_TXADRMAP_SET      = 37,

    /** Sets the Rx Address Map Size1 (RAMS1) register with a given
     *  address/value used in calculating the inbound packet address */
    CSL_VLYNQ_CMD_RAMS1_RXADRSIZE1_SET    = 38,
    /** Sets the Rx Address Map Offset1 (RAMO1) register with a given
     *  address/value used in calculating the inbound packet address */
    CSL_VLYNQ_CMD_RAMO1_RXADROFFSET1_SET  = 39,

    /** Sets the Rx Address Map Size2 (RAMS2) register with a given
     *  address/value used in calculating the inbound packet address */
    CSL_VLYNQ_CMD_RAMS2_RXADRSIZE2_SET    = 40,
    /** Sets the Rx Address Map Offset2 (RAMO2) register with a given
     *  address/value used in calculating the inbound packet address */
    CSL_VLYNQ_CMD_RAMO2_RXADROFFSET2_SET  = 41,

    /** Sets the Rx Address Map Size3 (RAMS3) register with a given
     *  address/value used in calculating the inbound packet address */
    CSL_VLYNQ_CMD_RAMS3_RXADRSIZE3_SET    = 42,
    /** Sets the Rx Address Map Offset3 (RAMO3) register with a given
     *  address/value used in calculating the inbound packet address */
    CSL_VLYNQ_CMD_RAMO3_RXADROFFSET3_SET  = 43,

    /** Sets the Rx Address Map Size4 (RAMS4) register with a given
     *  address/value used in calculating the inbound packet address */
    CSL_VLYNQ_CMD_RAMS4_RXADRSIZE4_SET    = 44,
    /** Sets the Rx Address Map Offset4 (RAMO4) register with a given
     *  address/value used in calculating the inbound packet address */
    CSL_VLYNQ_CMD_RAMO4_RXADROFFSET4_SET  = 45,

    /** Enable INTVEC0 (3-0) interrupt(s) */
    CSL_VLYNQ_CMD_INTVEC0_INT_ENA         = 46,
    /** Disable INTVEC0 (3-0) interrupt(s) */
    CSL_VLYNQ_CMD_INTVEC0_INT_DIS         = 47,

    /** INTVEC0s' Interrupt-3 type */
    CSL_VLYNQ_CMD_INTVEC0_INT3_TYPE_SET   = 48,
    /** INTVEC0s' Interrupt-3 polarity */
    CSL_VLYNQ_CMD_INTVEC0_INT3_POL_SET    = 49,
    /** INTVEC0's Interrupt-3 interrupt vector */
    CSL_VLYNQ_CMD_INTVEC0_INT3_INTVEC_SET = 50,

    /** INTVEC0s' Interrupt-2 type */
    CSL_VLYNQ_CMD_INTVEC0_INT2_TYPE_SET   = 51,
    /** INTVEC0s' Interrupt-2 polarity */
    CSL_VLYNQ_CMD_INTVEC0_INT2_POL_SET    = 52,
    /** INTVEC0's Interrupt-2 interrupt vector */
    CSL_VLYNQ_CMD_INTVEC0_INT2_INTVEC_SET = 53,

    /** INTVEC0s' Interrupt-1 type */
    CSL_VLYNQ_CMD_INTVEC0_INT1_TYPE_SET   = 54,
    /** INTVEC0s' Interrupt-1 polarity */
    CSL_VLYNQ_CMD_INTVEC0_INT1_POL_SET    = 55,
    /** INTVEC0's Interrupt-1 interrupt vector */
    CSL_VLYNQ_CMD_INTVEC0_INT1_INTVEC_SET = 56,

    /** INTVEC0s' Interrupt-0 type */
    CSL_VLYNQ_CMD_INTVEC0_INT0_TYPE_SET   = 57,
    /** INTVEC0s' Interrupt-0 polarity */
    CSL_VLYNQ_CMD_INTVEC0_INT0_POL_SET    = 58,
    /** INTVEC0's Interrupt-0 interrupt vector */
    CSL_VLYNQ_CMD_INTVEC0_INT0_INTVEC_SET = 59,

    /** Enable INTVEC1 (7-4) interrupt(s) */
    CSL_VLYNQ_CMD_INTVEC1_INT_ENA         = 60,
    /** Disable INTVEC1 (7-4) interrupt(s) */
    CSL_VLYNQ_CMD_INTVEC1_INT_DIS         = 61,

    /** INTVEC1s' Interrupt-7 type */
    CSL_VLYNQ_CMD_INTVEC1_INT7_TYPE_SET   = 62,
    /** INTVEC1s' Interrupt-7 polarity */
    CSL_VLYNQ_CMD_INTVEC1_INT7_POL_SET    = 63,
    /** INTVEC1's Interrupt-7 interrupt vector */
    CSL_VLYNQ_CMD_INTVEC1_INT7_INTVEC_SET = 64,

    /** INTVEC1s' Interrupt-6 type */
    CSL_VLYNQ_CMD_INTVEC1_INT6_TYPE_SET   = 65,
    /** INTVEC1s' Interrupt-6 polarity */
    CSL_VLYNQ_CMD_INTVEC1_INT6_POL_SET    = 66,
    /** INTVEC1's Interrupt-6 interrupt vector */
    CSL_VLYNQ_CMD_INTVEC1_INT6_INTVEC_SET = 67,

    /** INTVEC1s' Interrupt-5 type */
    CSL_VLYNQ_CMD_INTVEC1_INT5_TYPE_SET   = 68,
    /** INTVEC1s' Interrupt-5 polarity */
    CSL_VLYNQ_CMD_INTVEC1_INT5_POL_SET    = 69,
    /** INTVEC1's Interrupt-5 interrupt vector */
    CSL_VLYNQ_CMD_INTVEC1_INT5_INTVEC_SET = 70,

    /** INTVEC1s' Interrupt-4 type */
    CSL_VLYNQ_CMD_INTVEC1_INT4_TYPE_SET   = 71,
    /** INTVEC1s' Interrupt-4 polarity */
    CSL_VLYNQ_CMD_INTVEC1_INT4_POL_SET    = 72,
    /** INTVEC1's Interrupt-4 interrupt vector */
    CSL_VLYNQ_CMD_INTVEC1_INT4_INTVEC_SET = 73,

/** Commands for remote VLYNQs' configuration register */

    /** Disable remote VLYNQ Power Management */
    CSL_VLYNQ_CMD_REMOTE_PMEN_DIS       = 74,
    /** Enable remote VLYNQ Power Management */
    CSL_VLYNQ_CMD_REMOTE_PMEN_ENA       = 75,

    /** Enable remote VLYNQ Serial Clock Pull-up-disable */
    CSL_VLYNQ_CMD_REMOTE_SCLKPUDIS_ENA  = 76,
    /** Disable remote VLYNQ Serial Clock Pull-up-disable */
    CSL_VLYNQ_CMD_REMOTE_SCLKPUDIS_DIS  = 77,

    /** Set remote VLYNQ's RTM sample value */
    CSL_VLYNQ_CMD_REMOTE_RXSAMPLEVAL_SET = 78,

    /** Enable remote VLYNQs' RTM Write valid */
    CSL_VLYNQ_CMD_REMOTE_RTMVALIDWR_ENA = 79,
    /** Disable remote VLYNQ RTM Write valid
     *  (rxsample val will be invalid) */
    CSL_VLYNQ_CMD_REMOTE_RTMVALIDWR_DIS = 80,

    /** Enable remote VLYNQs' RTM (Receive Timing Manager) */
    CSL_VLYNQ_CMD_REMOTE_RTMENABLE_ENA  = 81,
    /** Disable remote VLYNQs' RTM (Receive Timing Manager) */
    CSL_VLYNQ_CMD_REMOTE_RTMENABLE_DIS  = 82,

    /** Selects remote VLYNQs' TX fast path */
    CSL_VLYNQ_CMD_REMOTE_TXFASTPATH_ENA = 83,
    /** Selects remote VLYNQs' TX Slow path */
    CSL_VLYNQ_CMD_REMOTE_TXFASTPATH_DIS = 84,

    /** Selects remote VLYNQs' Serial Clock divider value */
    CSL_VLYNQ_CMD_REMOTE_CLKDIV_SET     = 85,

    /** Remote VLYNQ clock is sourced externally */
    CSL_VLYNQ_CMD_REMOTE_CLKDIR_INPUT   = 86,
    /** Remote VLYNQ uses internal clock, divided down
     *  vesrion of vlynk_clk_ref */
    CSL_VLYNQ_CMD_REMOTE_CLKDIR_OUTPUT  = 87,

    /** In remote VLYNQ, forward/transmit Interrupt packets
     *  over serial-interface */
    CSL_VLYNQ_CMD_REMOTE_INTLOCAL_REMOTE = 88,
    /** In remote VLYNQ, post Interrupts locally */
    CSL_VLYNQ_CMD_REMOTE_INTLOCAL_LOCAL = 89,

    /** Disables remote VLYNQs' Status Interrupts */
    CSL_VLYNQ_CMD_REMOTE_INTENABLE_DIS  = 90,
    /** Enables remote VLYNQs' Status Interrupts */
    CSL_VLYNQ_CMD_REMOTE_INTENABLE_ENA  = 91,

    /* Razak: Added following 2 new command for writing to 'intvec'
     *  field of CTRL reg */
    /** Sets remote VLYNQs' intvec field */
    CSL_VLYNQ_CMD_REMOTE_INTVEC_SET     = 92,
    /** Clears remote VLYNQs' intvec field */
    CSL_VLYNQ_CMD_REMOTE_INTVEC_CLR     = 93,

    /** Disable remote VLYNQs' intcfg: Use INTPTR register
     *  as a pointer to memory */
    CSL_VLYNQ_CMD_REMOTE_INT2CFG_DIS    = 94,
    /** Enable remote VLYNQs' intcfg: Use INTPTR register as a
     *  pointer to Configuration register */
    CSL_VLYNQ_CMD_REMOTE_INT2CFG_ENA    = 95,

    /** Enable remote VLYNQs' Address Optimization */
    CSL_VLYNQ_CMD_REMOTE_AOPTDISABLE_ENA = 96,
    /** Disable remote VLYNQs' Address Optimization */
    CSL_VLYNQ_CMD_REMOTE_AOPTDISABLE_DIS = 97,

    /** Disable remote VLYNQs' internal loop-back */
    CSL_VLYNQ_CMD_REMOTE_ILOOP_DIS      = 98,
    /** Enable remote VLYNQs' internal loop-back */
    CSL_VLYNQ_CMD_REMOTE_ILOOP_ENA      = 99,

    /** Deassert remote VLYNQ's Soft RESET */
    CSL_VLYNQ_CMD_REMOTE_SOFTRESET_DEASSERT = 100,