csl_ataaux.h

TI达芬奇dm644x各硬件模块测试代码

 *   @n  The normal functional mode is selected.
 *
 *   @b Modifies
 *   @n ata TLGC register.
 *
 *   @b Example
 *   @verbatim
        CSL_AtaHandle      hAta;
        ...
        CSL_ataNormalModeEnable (hAta);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_ataNormalModeEnable (
    CSL_AtaHandle              hAta
)
{
    CSL_FINS(hAta->regs->IODFTM.TLGC, ATA_TLGC_ESEL, 1);
}

/** ============================================================================
 *   @n@b CSL_ataTestOutputEnable
 *
 *   @b Description
 *      Enable Test output
 *
 *   @b Arguments
 *   @verbatim
        hAta         Handle to the ATA instance
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  Test output is enabled.
 *
 *   @b Modifies
 *   @n ata TLGC register.
 *
 *   @b Example
 *   @verbatim
        CSL_AtaHandle      hAta;
        ...
        CSL_ataTestOutputEnable (hAta);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_ataTestOutputEnable (
    CSL_AtaHandle              hAta
)
{
    CSL_FINS(hAta->regs->IODFTM.TLGC, ATA_TLGC_TOEN, 0);
}

/** ============================================================================
 *   @n@b CSL_ataTestOutputDisable
 *
 *   @b Description
 *      Disable Test output
 *
 *   @b Arguments
 *   @verbatim
        hAta         Handle to the ATA instance
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  Test output is enabled.
 *
 *   @b Modifies
 *   @n ata TLGC register.
 *
 *   @b Example
 *   @verbatim
        CSL_AtaHandle      hAta;
        ...
        CSL_ataTestOutputDisable (hAta);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_ataTestOutputDisable (
    CSL_AtaHandle               hAta
)
{
    CSL_FINS(hAta->regs->IODFTM.TLGC, ATA_TLGC_TOEN, 1);
}

/** ============================================================================
 *   @n@b CSL_ataSetMisrState
 *
 *   @b Description
 *      Sets the MISR state
 *
 *   @b Arguments
 *   @verbatim
        hAta         Handle to the ATA instance
        loadVal      Value to be loaded into the register
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  MISR state is set.
 *
 *   @b Modifies
 *   @n ata TLGC register.
 *
 *   @b Example
 *   @verbatim
        CSL_AtaHandle      hAta;
        Uint8              loadVal;
        ...
        CSL_ataSetMisrState (hAta, loadVal);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_ataSetMisrState (
    CSL_AtaHandle          hAta,
    Uint8                  loadVal
)
{
    CSL_FINS(hAta->regs->IODFTM.TLGC, ATA_TLGC_MC, loadVal);
}

/**
 *  Hw Setup functions of ATA
 */

/** ============================================================================
 *   @n@b CSL_ataHwSetupControl
 *
 *   @b Description
 *      Setup hardware timing control.
 *
 *   @b Arguments
 *   @verbatim
        hAta          Handle to the ATA instance
        setupControl  Pointer to HwSetupTimingControl structure
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  Timing Control is set.
 *
 *   @b Modifies
 *   @n ata IDETIMP, IDETIMS, SIDETIM, UDMATIM registers depending on ataNum.
 *
 *   @b Example
 *   @verbatim
        CSL_AtaHandle                hAta;
        CSL_AtaHwSetupTimingControl  setupControl;
        ...
        CSL_ataHwSetupControl (hAta, &setupControl);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_ataHwSetupControl (
    CSL_AtaHandle                hAta,
    CSL_AtaHwSetupTimingControl *setupControl
)
{
    if (hAta->ataNum == CSL_ATA_PRIMARY) {
        CSL_FINS(hAta->regs->CONFIG.IDETIMP, ATA_IDETIMP_RDYSMPL,
                 setupControl->iordySamplePoint);
        CSL_FINS(hAta->regs->CONFIG.IDETIMP, ATA_IDETIMP_RDYRCVRY,
                 setupControl->iordyRecoveryTime);

        if (setupControl->slaveTimingEnable == CSL_ATA_ENABLE) {
            CSL_FINS(hAta->regs->CONFIG.SIDETIM, ATA_SIDETIM_RDYSMPP1,
                     setupControl->iordySamplePointSlave);
            CSL_FINS(hAta->regs->CONFIG.SIDETIM, ATA_SIDETIM_RDYRCYP1,
                     setupControl->iordyRecoveryTimeSlave);
        }
        CSL_FINS(hAta->regs->CONFIG.IDETIMP, ATA_IDETIMP_SLVTIMEN,
                 setupControl->slaveTimingEnable);

        CSL_FINS(hAta->regs->CONFIG.UDMATIM, ATA_UDMATIM_TCYCP0,
                 setupControl->udmaCycleTimeMaster);
        CSL_FINS(hAta->regs->CONFIG.UDMATIM, ATA_UDMATIM_TCYCP1,
                 setupControl->udmaCycleTimeSlave);
    }

    else if (hAta->ataNum == CSL_ATA_SECONDARY) {
        CSL_FINS(hAta->regs->CONFIG.IDETIMS, ATA_IDETIMS_RDYSMPL,
                 setupControl->iordySamplePoint);
        CSL_FINS(hAta->regs->CONFIG.IDETIMS, ATA_IDETIMS_RDYRCVRY,
                 setupControl->iordyRecoveryTime);

        if (setupControl->slaveTimingEnable == CSL_ATA_ENABLE) {
            CSL_FINS(hAta->regs->CONFIG.SIDETIM, ATA_SIDETIM_RDYSMPS1,
                     setupControl->iordySamplePointSlave);
            CSL_FINS(hAta->regs->CONFIG.SIDETIM, ATA_SIDETIM_RDYRCYS1,
                     setupControl->iordyRecoveryTimeSlave);
        }
        CSL_FINS(hAta->regs->CONFIG.IDETIMS, ATA_IDETIMS_SLVTIMEN,
                 setupControl->slaveTimingEnable);

        CSL_FINS(hAta->regs->CONFIG.UDMATIM, ATA_UDMATIM_TCYCS0,
                 setupControl->udmaCycleTimeMaster);
        CSL_FINS(hAta->regs->CONFIG.UDMATIM, ATA_UDMATIM_TCYCS1,
                 setupControl->udmaCycleTimeSlave);
    }
}

/** ============================================================================
 *   @n@b CSL_ataHwSetupCharacteristics
 *
 *   @b Description
 *      Set up hardware timing characteristics of the IDE cycle.
 *
 *   @b Arguments
 *   @verbatim
        hAta          Handle to the ATA instance
        setupChars    Pointer to HwSetupTimingChars structure
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  Timing Characteristics of the IDE cycle are set.
 *
 *   @b Modifies
 *   @n ata IDETIMP or IDETIMS registers depending on ataNum.
 *
 *   @b Example
 *   @verbatim
        CSL_AtaHandle                hAta;
        CSL_AtaHwSetupTimingChars    setupChars;
        ...
        CSL_ataHwSetupCharacteristics (hAta, &setupChars);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_ataHwSetupCharacteristics (
    CSL_AtaHandle                     hAta,
    CSL_AtaHwSetupTimingChars        *setupChars
)
{
    if (hAta->ataNum == CSL_ATA_PRIMARY) {

        register Uint32 reg_IDETIMP = hAta->regs->CONFIG.IDETIMP;

        CSL_FINS(reg_IDETIMP, ATA_IDETIMP_DMAFTIM0,
                 setupChars->dmaFastTimingMaster);
        CSL_FINS(reg_IDETIMP, ATA_IDETIMP_PREPOST0,
                 setupChars->pioPrefetchPostWriteMaster);
        CSL_FINS(reg_IDETIMP, ATA_IDETIMP_RDYSEN0,
                 setupChars->iordySamplePointMaster);
        CSL_FINS(reg_IDETIMP, ATA_IDETIMP_PIOFTIM0,
                 setupChars->pioFastTimingMaster);

        CSL_FINS(reg_IDETIMP, ATA_IDETIMP_DMAFTIM1,
                 setupChars->dmaFastTimingSlave);
        CSL_FINS(reg_IDETIMP, ATA_IDETIMP_PREPOST1,
                 setupChars->pioPrefetchPostWriteSlave);
        CSL_FINS(reg_IDETIMP, ATA_IDETIMP_RDYSEN1,
                 setupChars->iordySamplePointSlave);
        CSL_FINS(reg_IDETIMP, ATA_IDETIMP_PIOFTIM1,
                 setupChars->pioFastTimingSlave);

        hAta->regs->CONFIG.IDETIMP = reg_IDETIMP;

    }

    else if (hAta->ataNum == CSL_ATA_SECONDARY) {

        register Uint32 reg_IDETIMS = hAta->regs->CONFIG.IDETIMS;

        CSL_FINS(reg_IDETIMS, ATA_IDETIMS_DMAFTIM0,
                 setupChars->dmaFastTimingMaster);
        CSL_FINS(reg_IDETIMS, ATA_IDETIMS_PREPOST0,
                 setupChars->pioPrefetchPostWriteMaster);
        CSL_FINS(reg_IDETIMS, ATA_IDETIMS_RDYSEN0,
                 setupChars->iordySamplePointMaster);
        CSL_FINS(reg_IDETIMS, ATA_IDETIMS_PIOFTIM0,
                 setupChars->pioFastTimingMaster);

        CSL_FINS(reg_IDETIMS, ATA_IDETIMS_DMAFTIM1,
                 setupChars->dmaFastTimingSlave);
        CSL_FINS(reg_IDETIMS, ATA_IDETIMS_PREPOST1,
                 setupChars->pioPrefetchPostWriteSlave);
        CSL_FINS(reg_IDETIMS, ATA_IDETIMS_RDYSEN1,
                 setupChars->iordySamplePointSlave);
        CSL_FINS(reg_IDETIMS, ATA_IDETIMS_PIOFTIM1,
                 setupChars->pioFastTimingSlave);

        hAta->regs->CONFIG.IDETIMS = reg_IDETIMS;

    }
}

/** ============================================================================
 *   @n@b CSL_ataHwSetupOverride
 *
 *   @b Description
 *      Set up override configuration of ATA.
 *
 *   @b Arguments
 *   @verbatim
        hAta            Handle to the ATA instance
        setupOverride   Pointer to CSL_AtaHwSetupTimingOverride structure
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  Override configuration of ATA is set.
 *
 *   @b Modifies
 *   @n ata registers depending on ataNum.
 *
 *   @b Example
 *   @verbatim
        CSL_AtaHandle                 hAta;
        CSL_AtaHwSetupTimingOverride  setupOverride;
        ...
        CSL_ataHwSetupOverride (hAta, &setupOverride);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_ataHwSetupOverride (
    CSL_AtaHandle                 hAta,
    CSL_AtaHwSetupTimingOverride *setupOverride
)
{
    if (setupOverride->override == CSL_ATA_ENABLE) {
        if (hAta->ataNum == CSL_ATA_PRIMARY) {
            if (setupOverride->overriddenMaster != NULL) {
                CSL_AtaHwSetupTimingParams * setup =
                                               setupOverride->overriddenMaster;
                CSL_FINS(hAta->regs->CONFIG.REGSTB, ATA_REGSTB_REGSTB0P,
                         setup->regStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.REGRCVR, ATA_REGRCVR_REGRCV0P,
                         setup->regRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.DATSTB, ATA_DATSTB_DATSTB0P,
                         setup->dataStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.DATRCVR, ATA_DATRCVR_DATRCV0P,
                         setup->dataRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.DMASTB, ATA_DMASTB_DMASTB0P,
                         setup->dmaStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.DMARCVR, ATA_DMARCVR_DMARCV0P,
                         setup->dmaRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.UDMASTB, ATA_UDMASTB_UDMSTB0P,
                         setup->udmaStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.UDMATRP, ATA_UDMATRP_UDMTRP0P,
                         setup->udmaReadyToPause);
                CSL_FINS(hAta->regs->CONFIG.UDMATENV, ATA_UDMATENV_UDMTNV0P,
                         setup->udmaEnvelopeTime);
                CSL_FINS(hAta->regs->CONFIG.MISCCTL, ATA_MISCCTL_HWNHLD0P,
                         setup->writeDataHoldTime);
            }

            if (setupOverride->overriddenSlave != NULL) {
                CSL_AtaHwSetupTimingParams * setup =
                                               setupOverride->overriddenSlave;
                CSL_FINS(hAta->regs->CONFIG.REGSTB, ATA_REGSTB_REGSTB1P,
                         setup->regStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.REGRCVR, ATA_REGRCVR_REGRCV1P,
                         setup->regRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.DATSTB, ATA_DATSTB_DATSTB1P,
                         setup->dataStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.DATRCVR, ATA_DATRCVR_DATRCV1P,
                         setup->dataRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.DMASTB, ATA_DMASTB_DMASTB1P,
                         setup->dmaStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.DMARCVR, ATA_DMARCVR_DMARCV1P,
                         setup->dmaRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.UDMASTB, ATA_UDMASTB_UDMSTB1P,
                         setup->udmaStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.UDMATRP, ATA_UDMATRP_UDMTRP1P,
                         setup->udmaReadyToPause);
                CSL_FINS(hAta->regs->CONFIG.UDMATENV, ATA_UDMATENV_UDMTNV1P,
                         setup->udmaEnvelopeTime);
                CSL_FINS(hAta->regs->CONFIG.MISCCTL, ATA_MISCCTL_HWNHLD1P,
                         setup->writeDataHoldTime);
            }
        }

        else if (hAta->ataNum == CSL_ATA_SECONDARY) {
            if (setupOverride->overriddenMaster != NULL) {
                CSL_AtaHwSetupTimingParams * setup =
                                               setupOverride->overriddenMaster;
                CSL_FINS(hAta->regs->CONFIG.REGSTB, ATA_REGSTB_REGSTB0S,
                         setup->regStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.REGRCVR, ATA_REGRCVR_REGRCV0S,
                         setup->regRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.DATSTB, ATA_DATSTB_DATSTB0S,
                         setup->dataStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.DATRCVR, ATA_DATRCVR_DATRCV0S,
                         setup->dataRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.DMASTB, ATA_DMASTB_DMASTB0S,
                         setup->dmaStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.DMARCVR, ATA_DMARCVR_DMARCV0S,
                         setup->dmaRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.UDMASTB, ATA_UDMASTB_UDMSTB0S,
                         setup->udmaStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.UDMATRP, ATA_UDMATRP_UDMTRP0S,
                         setup->udmaReadyToPause);
                CSL_FINS(hAta->regs->CONFIG.UDMATENV, ATA_UDMATENV_UDMTNV0S,
                         setup->udmaEnvelopeTime);
                CSL_FINS(hAta->regs->CONFIG.MISCCTL, ATA_MISCCTL_HWNHLD0S,
                         setup->writeDataHoldTime);
            }

            if (setupOverride->overriddenSlave != NULL) {
                CSL_AtaHwSetupTimingParams * setup =
                                               setupOverride->overriddenSlave;
                CSL_FINS(hAta->regs->CONFIG.REGSTB, ATA_REGSTB_REGSTB1S,
                         setup->regStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.REGRCVR, ATA_REGRCVR_REGRCV1S,
                         setup->regRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.DATSTB, ATA_DATSTB_DATSTB1S,
                         setup->dataStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.DATRCVR, ATA_DATRCVR_DATRCV1S,
                         setup->dataRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.DMASTB, ATA_DMASTB_DMASTB1S,
                         setup->dmaStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.DMARCVR, ATA_DMARCVR_DMARCV1S,
                         setup->dmaRecoveryTime);
                CSL_FINS(hAta->regs->CONFIG.UDMASTB, ATA_UDMASTB_UDMSTB1S,
                         setup->udmaStrobeWidth);
                CSL_FINS(hAta->regs->CONFIG.UDMATRP, ATA_UDMATRP_UDMTRP1S,
                         setup->udmaReadyToPause);
                CSL_FINS(hAta->regs->CONFIG.UDMATENV, ATA_UDMATENV_UDMTNV1S,
                         setup->udmaEnvelopeTime);
                CSL_FINS(hAta->regs->CONFIG.MISCCTL, ATA_MISCCTL_HWNHLD1S,
                         setup->writeDataHoldTime);
            }
        }
    }

    CSL_FINS(hAta->regs->CONFIG.MISCCTL, ATA_MISCCTL_TIMORIDE,
             setupOverride->override);
}

/** ============================================================================
 *   @n@b CSL_ataHwSetupResetControl
 *
 *   @b Description
 *      Set up Reset Control of ATA.
 *
 *   @b Arguments
 *   @verbatim
        hAta               Handle to the ATA instance
        setupResetControl  Pointer to CSL_AtaHwSetupResetControl structure
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  Reset Control of ATA is set.
 *
 *   @b Modifies
 *   @n ata MISCCTL register.
 *
 *   @b Example
 *   @verbatim
        CSL_AtaHandle                 hAta;
        CSL_AtaHwSetupResetControl    setupResetControl;
        ...
        CSL_ataHwSetupResetControl (hAta, &setupResetControl);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_ataHwSetupResetCont