csl_ata.h

TI达芬奇dm644x各硬件模块测试代码

    Uint32 misr2;  /**< MISR 2 value */
    Uint32 misr3;  /**< MISR 3 value */
} CSL_AtaIodftMisr;

/**
 * @brief       The various timing parameters
 *
 * The structure groups the various timing parameters for IDE-Task File register
 * accesses, PIO-data accesses, Multi-word DMA accesses and Ultra DMA transfers.
 * This is typically used when the controller needs to be configured to override
 * the default timing control settings.
 */
typedef struct {

    Uint8     regStrobeWidth;   /**< 8-bit Task File Register Access Strobe
                                  Width in number of cycles : 1 to 128 */
    Uint8     regRecoveryTime;  /**< 8-bit Task File Register Access Recovery
                                  Time in number of cycles : 1 to 128 */

    Uint8     dataStrobeWidth;  /**< 16-bit PIO Data Access Strobe Width in
                                  number of cycles : 1 to 128 */
    Uint8     dataRecoveryTime; /**< 16-bit PIO Data Access Recovery Time in
                                  number of cycles : 1 to 128 */

    Uint8     dmaStrobeWidth;   /**< Multi-word DMA Access Strobe Width in
                                  number of cycles : 1 to 128 */
    Uint8     dmaRecoveryTime;  /**< Multi-word DMA Access Recovery Time in
                                  number of cycles : 1 to 128 */

    Uint8     udmaStrobeWidth;  /**< Ultra-DMA Access Strobe Width in number of
                                  cycles : 1 to 16 */
    Uint8     udmaReadyToPause; /**< Ultra-DMA Access Ready-to-Pause Time in
                                  number of cycles : 1 to 32 */
    Uint8     udmaEnvelopeTime; /**< Ultra-DMA Access Envelope Time in number of
                                  cycles : 1 to 16 */
    Uint8     writeDataHoldTime;/**< Write Data Hold Time for Task File writes,
                                  PIO writes & multi-word DMA writes */

} CSL_AtaHwSetupTimingParams;

/**
 * @brief       Defaults set of values for timing parameters
 */
#define CSL_ATA_HWSETUP_TIMINGPARAMS_DEFAULTS   {   \
    /* .regStrobeWidth      = */ 1,                 \
    /* .regRecoveryTime     = */ 1,                 \
    /* .dataStrobeWidth     = */ 1,                 \
    /* .dataRecoveryTime    = */ 1,                 \
    /* .dmaStrobeWidth      = */ 1,                 \
    /* .dmaRecoveryTime     = */ 1,                 \
    /* .udmaStrobeWidth     = */ 1,                 \
    /* .udmaReadyToPause    = */ 1,                 \
    /* .udmaEnvelopeTime    = */ 1,                 \
    /* .writeDataHoldTime   = */ 1                  \
}

/**
 * @brief       Timing Override Configuration
 *
 * This structure could be used to override the timing control settings in cases
 * when the IDE clock frequency is not among the ones (33, 66, 100 or 133 MHz)
 * the Host Controller is pre-configured for.
 * Note: The 'overridden{Master,Slave}' members would be ignored if the
 * 'override' member is not enabled.
 */
typedef struct {
    CSL_AtaEnableDisable            override; /**< Enable/disable overriding
                                        of timing control settings */
    CSL_AtaHwSetupTimingParams *    overriddenMaster; /**< Overridden timing
                                        parameters for Master */
    CSL_AtaHwSetupTimingParams *    overriddenSlave; /**< Overridden timing
                                        parameters for Slave */
} CSL_AtaHwSetupTimingOverride;

/**
 * @brief       Defaults set of values for timing override configuration
 */
#define CSL_ATA_HWSETUP_TIMINGOVERRIDE_DEFAULTS   { \
    /* .override            = */ CSL_ATA_DISABLE,   \
    /* .overriddenMaster    = */ NULL,              \
    /* .overriddenSlave     = */ NULL               \
}

/**
 * @brief       Timing Control settings for pre-configured clock frequencies
 *
 * This structure could be used to configure the various parameters that
 * determine the PIO, DMA and UDMA modes of operation if the core is clocked at
 * one of the frequencies (33, 66, 100 or 133 MHz) the controller is configured
 * for.
 * Note: If the 'slaveTimingEnable' parameter is not enabled, the timing
 * behaviour for both the Master and the Slave devices are determined by
 * 'iordySamplePoint' and 'iordyRecoveryTime'. If 'slaveTimingEnable' is
 * enabled, 'iordyRecoveryTime' and 'iordySamplePoint' specify the timing
 * behaviour for the Master while 'iordyRecoveryTimeSlave' and
 * 'iordySamplePointSlave' specify those for the Slave.
 */
typedef struct {

    CSL_AtaIordySamplePoint         iordySamplePoint; /**< IORDY Sample Point
                                        for Master (and Slave; see Note) */
    CSL_AtaIordyRecoveryPoint       iordyRecoveryTime; /**< IORDY Recovery Point
                                        for Master (and Slave; see Note) */

    CSL_AtaEnableDisable            slaveTimingEnable; /**< Enable independent
                                        timing characteristics for the Slave */

    CSL_AtaIordySamplePoint         iordySamplePointSlave; /**< IORDY Sample
                                        Point for Slave (see Note) */
    CSL_AtaIordyRecoveryPoint       iordyRecoveryTimeSlave;/**< IORDY Recovery
                                        Point for Slave (see Note) */

    CSL_AtaUdmaCycleTime            udmaCycleTimeMaster; /**< Ultra-DMA
                                        Operation Mode for Master */
    CSL_AtaUdmaCycleTime            udmaCycleTimeSlave; /**< Ultra-DMA
                                        Operation Mode for Slave */

} CSL_AtaHwSetupTimingControl;

/**
 * @brief       Defaults set of values for timing control settings
 */
#define CSL_ATA_HWSETUP_TIMINGCONTROL_DEFAULTS   {                      \
    /* .iordySamplePoint        = */ CSL_ATA_IORDYSAMPLEPOINT_120NS,    \
    /* .iordyRecoveryTime       = */ CSL_ATA_IORDYRECOVERYPOINT_120NS,  \
    /* .slaveTimingEnable       = */ CSL_ATA_DISABLE,                   \
    /* .iordySamplePointSlave   = */ CSL_ATA_IORDYSAMPLEPOINT_120NS,    \
    /* .iordyRecoveryTimeSlave  = */ CSL_ATA_IORDYRECOVERYPOINT_120NS,  \
    /* .udmaCycleTimeMaster     = */ CSL_ATA_UDMACYCLETIME_MODE0,       \
    /* .udmaCycleTimeSlave      = */ CSL_ATA_UDMACYCLETIME_MODE0,       \
}

/**
 * @brief       Timing Characteristics configuration
 *
 * This structure could be used to configure the timing characteristics of the
 * IDE cycle for PIO and Bus Master Transfers.
 */
typedef struct {

    CSL_AtaEnableDisable    dmaFastTimingMaster; /**< DMA Fast Timing for
                                                   Master */
    CSL_AtaEnableDisable    pioFastTimingMaster; /**< PIO Fast Timing for
                                                   Master */
    CSL_AtaEnableDisable    pioPrefetchPostWriteMaster; /**< PIO Prefetch and
                                                 Postwrite feature for Master */
    CSL_AtaEnableDisable    iordySamplePointMaster; /**< IORDY Sample Point for
                                                      Master */

    CSL_AtaEnableDisable    dmaFastTimingSlave; /**< DMA Fast Timing for
                                                  Slave */
    CSL_AtaEnableDisable    pioFastTimingSlave; /**< PIO Fast Timing for
                                                  Slave */
    CSL_AtaEnableDisable    pioPrefetchPostWriteSlave; /**< PIO Prefetch and
                                                 Post-write feature for Slave */
    CSL_AtaEnableDisable    iordySamplePointSlave; /**< IORDY Sample Point for
                                                  Slave */

} CSL_AtaHwSetupTimingChars;

/**
 * @brief       Defaults set of values for timing characteristics configuration
 */
#define CSL_ATA_HWSETUP_TIMINGCHARS_DEFAULTS    {           \
    /* .dmaFastTimingMaster         = */ CSL_ATA_DISABLE,   \
    /* .pioFastTimingMaster         = */ CSL_ATA_DISABLE,   \
    /* .pioPrefetchPostWriteMaster  = */ CSL_ATA_DISABLE,   \
    /* .iordySamplePointMaster      = */ CSL_ATA_DISABLE,   \
    /* .dmaFastTimingSlave          = */ CSL_ATA_DISABLE,   \
    /* .pioFastTimingSlave          = */ CSL_ATA_DISABLE,   \
    /* .pioPrefetchPostWriteSlave   = */ CSL_ATA_DISABLE,   \
    /* .iordySamplePointSlave       = */ CSL_ATA_DISABLE    \
}

/**
 * @brief       Reset Control configuration
 */
typedef struct {
    CSL_AtaResetMode                resetPinMode;   /**< Reset Pin Mode */
    CSL_AtaResetSignal              resetPinSignal; /**< Reset Pin Signal */
} CSL_AtaHwSetupResetControl;

/**
 * @brief       Defaults set of values for reset control configuration
 */
#define CSL_ATA_HWSETUP_RESETCONTROL_DEFAULTS    {          \
    /* .resetPinMode    = */ CSL_ATA_RESETMODE_OPENCOLL,    \
    /* .resetPinSignal  = */ CSL_ATA_RESETSIGNAL_NEGATED    \
}

/**
 * @brief       Miscellaneous configuration
 */
typedef struct {
    Uint32  iordyTimeout; /**< IORDY Timeout */
    Uint16  slewRateControl;    /**< Slew Rate Control */
} CSL_AtaHwSetupMisc;

/**
 * @brief   Defaults set of values for miscellaneous configuration parameters
 */

#define CSL_ATA_HWSETUP_MISC_DEFAULTS    {  \
    /* .iordyTimeout      = */   0,         \
    /* .slewRateControl   = */   0x0155     \
}

/**
 * @brief       DMA configuration
 */
typedef struct {
    CSL_AtaDmaMode  dmaModeMaster;  /**< Multi-Word DMA or Ultra-DMA transfer
                                      mode for Master */
    CSL_AtaDmaMode  dmaModeSlave;   /**< Multi-Word DMA or Ultra-DMA transfer
                                      mode for Slave */
    void *          dmaDescTable;   /**< DMA descriptor table base */
} CSL_AtaHwSetupDma;

/**
 * @brief       Defaults for DMA setup structure
 */
#define CSL_ATA_HWSETUP_DMA_DEFAULTS    {               \
    /* .dmaModeMaster = */ CSL_ATA_DMAMODE_MULTIWORD,   \
    /* .dmaModeSlave  = */ CSL_ATA_DMAMODE_MULTIWORD,   \
    /* .dmaDescTable  = */ NULL                         \
}

/**
 * @brief       ATA Controller configuration parameters
 *
 * The ATA Controller could be configured by appropriately populating this
 * structure before invoking the CSL_ataHwSetup(..) API.
 * Note: This structure contains pointers to other structures that group
 * together related configuration elements. If the user does not wish to make
 * use of a particular group, s/he may NULL the correponding pointers, before
 * passing it to the CSL_ata{HwSetup,GetHwSetup} APIs.
 */
typedef struct {
    CSL_AtaHwSetupTimingControl     *control;         /**< Timing Control
                                                       configuration */
    CSL_AtaHwSetupTimingChars       *characteristics; /**< Timing
                                                       Characteristics
                                                       configuration */
    CSL_AtaHwSetupTimingOverride    *override;        /**< Timing Override
                                                       settings */

    CSL_AtaHwSetupDma              *dma;             /**< DMA configuration */

    CSL_AtaHwSetupResetControl     *resetControl;    /**< Reset Control
                                                       configuration */
    CSL_AtaHwSetupMisc             *misc;            /**< Miscellaneous
                                                       configuration */
} CSL_AtaHwSetup;

/**
 * @brief       Defaults for the setup-structure
 */
#define CSL_ATA_HWSETUP_DEFAULTS    {       \
    /* .control         = */    NULL,       \
    /* .characteristics = */    NULL,       \
    /* .override        = */    NULL,       \
    /* .dma             = */    NULL,       \
    /* .resetControl    = */    NULL,       \
    /* .misc            = */    NULL        \
}

/**
 * @brief Config-structure
 *
 * Used to configure the ATA CSL_ataHwSetupRaw()
 */
typedef struct {

    /* Hardware Setup Raw for DMA Engine Registers */

    volatile Uint16 BMICP;    /**< Primary IDE Channel DMA Control */
    volatile Uint16 BMISP;    /**< Primary IDE Channel DMA Status */
    volatile Uint32 BMIDTPP;  /**< Primary Channel DMA Descriptor Pointer */
    volatile Uint16 BMICS;    /**< Secondary IDE Channel DMA Control */
    volatile Uint16 BMISS;    /**< Secondary IDE Channel DMA Status */
    volatile Uint32 BMIDTPS;  /**< Secondary Channel DMA Descriptor Pointer */
    volatile Uint32 DMARXCNT; /**< DMA Transfer Bytes Received Count Reg */
    volatile Uint32 DMATXCNT; /**< DMA Transfer Bytes Transmitted Count Reg */

    /* Hardware Setup Raw for Config Registers */

    volatile Uint16 IDETIMP;   /**< Primary IDE Channel Timing register */
    volatile Uint16 IDETIMS;   /**< Secondary IDE Channel Timing register */
    volatile Uint8  SIDETIM;   /**< Slave IDE Timing Register */
    volatile Uint8  SLEWCTL_L; /**< IDE Slew Control Register: Lower byte */
    volatile Uint8  SLEWCTL_H; /**< IDE Slew Control Register: Higher byte */
    volatile Uint16 UDMACTL;   /**< Ultra DMA Control Register */
    volatile Uint16 UDMATIM;   /**< Ultra DMA Timing Register */
    volatile Uint32 MISCCTL;   /**< Miscellaneous Control Register */
    volatile Uint32 REGSTB;    /**< Task File Register Strobe Timing Register */
    volatile Uint32 REGRCVR;   /**< Task File Register Recovery Timing
                                    Register */
    volatile Uint32 DATSTB;    /**< Data Register PIO Strobe Timing Register */
    volatile Uint32 DATRCVR;   /**< Data Register PIO Recovery Timing
                                    Register */
    volatile Uint32 DMASTB;    /**< DMA Strobe Timing Register */
    volatile Uint32 DMARCVR;   /**< DMA Recovery Timing Register */
    volatile Uint32 UDMASTB;   /**< Ultra DMA Strobe Timing Register */
    volatile Uint32 UDMATRP;   /**< Ultra DMA Ready-to-Stop Timing Register */
    volatile Uint32 UDMATENV;  /**< Ultra DMA Timing Envelope Register */
    volatile Uint32 IORDYTMP;  /**< Primary IO Ready Timer Configuration
                                    Register */
    volatile Uint32 IORDYTMS;  /**< Secondary IO Ready Timer Configuration
                                    Register */

    /* Hardware Setup Raw for IODFTM Registers */

    volatile Uint32 TLGC;  /**< Test Logic Global Control Register */
    volatile Uint32 TLMR;  /**< Test Logic MISR Results Register */
    volatile Uint32 TLMR2; /**< Test Logic MISR Results 2 Register */
    volatile Uint32 TLMR3; /**< Test Logic MISR Results 3 Register */
    volatile Uint32 TLEC;  /**< Test Logic Execution Counter */
} CSL_AtaConfig;

/**
 * @brief       Defaults for the Config-structure
 */
#define CSL_ATA_CONFIG_DEFAULTS {  \
    /* Primary IDE Channel DMA Control */          CSL_ATA_BMICP_RESETVAL,     \
    /* Primary IDE Channel DMA Status */           CSL_ATA_BMISP_RESETVAL,     \
    /* Primary Channel DMA Descriptor Pointer */   CSL_ATA_BMIDTPP_RESETVAL,   \
    /* Secondary IDE Channel DMA Control */        CSL_ATA_BMICS_RESETVAL,     \
    /* Secondary IDE Channel DMA Status */         CSL_ATA_BMISS_RESETVAL,     \
    /* Secondary Channel DMA Descriptor Pointer */ CSL_ATA_BMIDTPS_RESETVAL,   \
    /* DMA Transfer Bytes Received Count Reg */    CSL_ATA_DMARXCNT_RESETVAL,  \
    /* DMA Transfer Bytes Transmitted Count Reg */ CSL_ATA_DMATXCNT_RESETVAL,  \
    /* Primary IDE Channel Timing Reg */           CSL_ATA_IDETIMP_RESETVAL,   \
    /* Secondary IDE Channel Timing Reg */         CSL_ATA_IDETIMS_RESETVAL,   \
    /* Slave IDE Timing Reg */                     CSL_ATA_SIDETIM_RESETVAL,   \
    /* IDE Slew Control Reg: Lower byte */         CSL_ATA_SLEWCTL_L_RESETVAL, \
    /* IDE Slew Control Reg: Higher byte */        CSL_ATA_SLEWCTL_H_RESETVAL, \
    /* Ultra DMA Control Reg */                    CSL_ATA_UDMACTL_RESETVAL,   \
    /* Ultra DMA Timing Reg */                     CSL_ATA_UDMATIM_RESETVAL,   \
    /* Miscellaneous Control Reg */                CSL_ATA_MISCCTL_RESETVAL,   \
    /* Task File Register Strobe Timing Reg */     CSL_ATA_REGSTB_RESETVAL,    \
    /* Task File Register Recovery Timing Reg */   CSL_ATA_REGRCVR_RESETVAL,   \
    /* Data Register PIO Strobe Timing Reg */      CSL_ATA_DATSTB_RESETVAL,    \
    /* Data Register PIO Recovery Timing Reg */    CSL_ATA_DATRCVR_RESETVAL,   \
    /* DMA Strobe Timing Reg */                    CSL_ATA_DMASTB_RESETVAL,    \
    /* DMA Recovery Timing Reg */                  CSL_ATA_DMARCVR_RESETVAL,   \
    /* Ultra DMA Strobe Timing Reg */              CSL_ATA_UDMASTB_RESETVAL,   \
    /* Ultra DMA Ready-to-Stop Timing Reg */       CSL_ATA_UDMATRP_RESETVAL,   \
    /* Ultra DMA Timing Envelope Reg */            CSL_ATA_UDMATENV_RESETVAL,  \
    /* Primary IO Ready Tmr Configuration Reg */   CSL_ATA_IORDYTMP_RESETVAL,  \
    /* Secondary IO Ready Tmr Configuration Reg */ CSL_ATA_IORDYTMS_RESETVAL,  \
    /* Test Logic Global Control Reg */            CSL_ATA_TLGC_RESETVAL,      \
    /* Test Logic MISR Results Reg */              CSL_ATA_TLMR_RESETVAL,      \
    /* Test Logic MISR Results 2 Reg */            CSL_ATA_TLMR2_RESETVAL,     \
    /* Test Logic MISR Results 3 Reg */            CSL_ATA_TLMR3_RESETVAL,     \
    /* Test Logic Execution Counter */             CSL_ATA_TLEC_RESETVAL       \
}

/** @brief Module specific context information. Present implementation of
 *         ATA CSL doesn't have any context information.
 */
typedef struct {
    /** Context information of ATA CSL.
     *  The below declaration is just a place-holder for future implementation.
     */