csl_ata.h

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/** @file csl_ata.h
 *
 *  @brief CSL functional-layer header file for the ATA module
 *
 *  Description
 *  - Comprises the function declarations for the various APIs and the
 *    associated enumerations, type and symbol definitions for the ATA
 *    module.
 *
 *  Path: \\(CSLPATH)\\ipmodules\\ata\\src
 *
 *  Modification 1
 *  - modified on: 2004/03/08
 *  - reason: creation
 *
 *  Date 2004/03/08
 *  Author RG Kiran
 */

/**
 * @mainpage ATA Controller Module
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for the
 * ATA Module across various devices. The CSL developer is expected to refer to
 * this document while designing APIs for these modules. Some of the APIs listed
 * here may not be applicable to a given ATA module. While in other cases this
 * list of APIs may not be sufficient cover all the features of a particular
 * module. The CSL developer should use his/her discretion in designing new APIs
 * or extending the existing ones to cover these.
 *
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL: Chip Support Library
 *   -# API: Application Programming Interface
 *   -# ATA: AT (Advanced Technology) Attachment
 *   -# ATAPI: ATA with Packet Interface extension
 *   -# IDE: Integrated Drive Electronics
 *
 * @subsection References
 *    -# CSL 3.x Technical Requirements Specification v0.5 (2003/05/14)
 *    http://www.india.ti.com/CatApps/CSL/3x/csl3x_archTRS.doc
 *    -# CSL 3.x Design Specification v1.03:
 *    http://www.india.ti.com/CatApps/CSL/3x/csl3x_design.pdf
 *    -# ATA Controller Specification: "BK-3710 -- IDE Host Controller Users
 *       Guide"
 *    http://dspdesign.india.ti.com/twiki/pub/Trinity/IDEATAATAPIInterface/
 *           BK-3710HU-2.0.pdf
 *    -# ATA Protocol Specification : "T13 1153D" rev18 (1998/08/19)
 *    http://www.t13.org/project/d1153r18.pdf
 *
 * @subsection Assumptions
 *     The abbreviation IDE and ATA has been used interchangingly to refer to
 *     the IDE/ATA protocol, device or controller. The context would usually
 *     make the sense clear.
 */

/* =============================================================================
 *  Revision History
 *  ===============
 *  07-Nov-2004 kpn Updated according to new cslr_ata.h file, which is generated
 *                  according to ti-3710shu-1.03 document
 *  08-Oct-2004 kpn Updated according to review comments
 *  27-Sep-2004 kpn Updated according to CSL upgradation guidelines.
 *  ============================================================================
 */

#ifndef _CSL_ATA_H_
#define _CSL_ATA_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <soc.h>
#include <csl_error.h>
#include <csl.h>
#include <csl_types.h>
#include <cslr_ata.h>

/*  ATA global macro declarations
 */

/** @brief ATA Primary Instance Command registers address
 */
#define CSL_ATA_CMDREGS_PRIMARY     ((Uint8 *) 0x345F0)

/** @brief ATA Primary Instance Control registers address
 */
#define CSL_ATA_CTLREGS_PRIMARY     ((Uint8 *) 0x347F6)

/** @brief ATA Secondary Instance Command registers address
 */
#define CSL_ATA_CMDREGS_SECONDARY   ((Uint8 *) 0x34570)

/** @brief ATA Secondary Instance Control registers address
 */
#define CSL_ATA_CTLREGS_SECONDARY   ((Uint8 *) 0x34776)

/*  ATA global typedef declarations
 */

/**
 * @brief       Common enumeration for enable/disable
 *
 * Standard module-wide enumeration for parameters that can either be in an
 * enabled or a disabled state.
 */
typedef enum {
    CSL_ATA_DISABLE = 0,    /**< Disable */
    CSL_ATA_ENABLE  = 1     /**< Enable */
} CSL_AtaEnableDisable;

/**
 * @brief       IORDY Sample Point
 */
typedef enum {
    CSL_ATA_IORDYSAMPLEPOINT_120NS  = 0,    /**< 120ns */
    CSL_ATA_IORDYSAMPLEPOINT_100NS  = 1,    /**< 100ns */
    CSL_ATA_IORDYSAMPLEPOINT_80NS   = 2,    /**<  80ns */
    CSL_ATA_IORDYSAMPLEPOINT_70NS   = 3     /**<  70ns */
} CSL_AtaIordySamplePoint;

/**
 * @brief       IORDY Recovery Point
 */
typedef enum {
    CSL_ATA_IORDYRECOVERYPOINT_120NS    = 0,    /**< 120ns */
    CSL_ATA_IORDYRECOVERYPOINT_100NS    = 1,    /**< 100ns */
    CSL_ATA_IORDYRECOVERYPOINT_75NS     = 2,    /**<  75ns */
    CSL_ATA_IORDYRECOVERYPOINT_50NS     = 3     /**<  50ns */
} CSL_AtaIordyRecoveryPoint;

/**
 * @brief       Ultra-DMA Mode of Operation
 */
typedef enum {
    CSL_ATA_UDMACYCLETIME_MODE0     = 0,    /**< Mode 0 */
    CSL_ATA_UDMACYCLETIME_MODE1     = 1,    /**< Mode 1 */
    CSL_ATA_UDMACYCLETIME_MODE2     = 2,    /**< Mode 2 */
    CSL_ATA_UDMACYCLETIME_MODE3     = 3,    /**< Mode 3 */
    CSL_ATA_UDMACYCLETIME_MODE4     = 4,    /**< Mode 4 */
    CSL_ATA_UDMACYCLETIME_MODE5     = 5,    /**< Mode 5 */
    CSL_ATA_UDMACYCLETIME_MODE6     = 6     /**< Mode 6 */
} CSL_AtaUdmaCycleTime;

/**
 * @brief       Multi-World DMA or Ultra-DMA Mode
 */
typedef enum {
    CSL_ATA_DMAMODE_MULTIWORD   = 0,    /**< Multi-Word DMA */
    CSL_ATA_DMAMODE_UDMA        = 1     /**< Ultra-DMA */
} CSL_AtaDmaMode;

/**
 * @brief       Reset Pin Drive Mode
 */
typedef enum {
    CSL_ATA_RESETMODE_OPENCOLL  = 0,    /**< Open Collector mode */
    CSL_ATA_RESETMODE_PUSHPULL  = 1     /**< Push Pull mode */
} CSL_AtaResetMode;

/**
 * @brief       Reset Pin Signal
 */
typedef enum {
    CSL_ATA_RESETSIGNAL_NEGATED     = 0,    /**< Negated ("high voltage") */
    CSL_ATA_RESETSIGNAL_ASSERTED    = 1     /**< Asserted ("low voltage") */
} CSL_AtaResetSignal;

/**
 * @brief       Enumeration of Control Registers that are writable
 */
typedef enum {
    CSL_ATA_CTLREGWR_DEVICECONTROL   =   0   /**< Device Control */
} CSL_AtaCtlRegWr;

/**
 * @brief       Enumeration of Control Registers that are readable
 */
typedef enum {
    CSL_ATA_CTLREGRD_ALTERNATESTATUS =   0   /**< Alternate Status */
} CSL_AtaCtlRegRd;

/**
 * @brief       Enumeration of Command Registers that are writable
 */
typedef enum {

    CSL_ATA_CMDREGWR_DATA            =   0,  /**< Data register */
    CSL_ATA_CMDREGWR_FEATURES        =   1,  /**< Features register */
    CSL_ATA_CMDREGWR_SECTORCOUNT     =   2,  /**< Sector Count register */
    CSL_ATA_CMDREGWR_SECTORNUMBER    =   3,  /**< Sector Number register */
    CSL_ATA_CMDREGWR_CYLINDERLOW     =   4,  /**< Cylinder Low register */
    CSL_ATA_CMDREGWR_CYLINDERHIGH    =   5,  /**< Cylinder High register */
    CSL_ATA_CMDREGWR_DEVICEHEAD      =   6,  /**< Device Head register */
    CSL_ATA_CMDREGWR_COMMAND         =   7,  /**< Command register */

    /* ATAPI */
    CSL_ATA_CMDREGWR_BYTECOUNTLOW    =   4,  /**< Byte Count Low register */
    CSL_ATA_CMDREGWR_BYTECOUNTHIGH   =   5   /**< Byte Count High register */

} CSL_AtaCmdRegWr;

/**
 * @brief       Enumeration of Command Registers that are readable
 */
typedef enum {

    CSL_ATA_CMDREGRD_DATA            =   0,  /**< Data register */
    CSL_ATA_CMDREGRD_ERROR           =   1,  /**< Error register */
    CSL_ATA_CMDREGRD_SECTORCOUNT     =   2,  /**< Sector Count register */
    CSL_ATA_CMDREGRD_SECTORNUMBER    =   3,  /**< Sector Number register */
    CSL_ATA_CMDREGRD_CYLINDERLOW     =   4,  /**< Cylinder Low register */
    CSL_ATA_CMDREGRD_CYLINDERHIGH    =   5,  /**< Cylinder High register */
    CSL_ATA_CMDREGRD_DEVICEHEAD      =   6,  /**< Device Head register */
    CSL_ATA_CMDREGRD_STATUS          =   7,  /**< Status register */

    /* ATAPI */
    CSL_ATA_CMDREGRD_INTERRUPTREASON =   3,  /**< Interrupt Reason register */
    CSL_ATA_CMDREGRD_BYTECOUNTLOW    =   4,  /**< Byte Count Low register */
    CSL_ATA_CMDREGRD_BYTECOUNTHIGH   =   5   /**< Byte Count High register */

} CSL_AtaCmdRegRd;

/**
 * @brief      Encapsulation of all writable Command Registers
 *
 * This structure should be instantiated and initialized with required
 * Command Register values and passed to the CSL_ataWriteCommandRegs function,
 * so that they get written to the corresponding register on the device.
 */
typedef struct {
    Uint16      DATA;            /**< Data register */
    Uint8       FEATURES;        /**< Features register */
    Uint8       SECTORCOUNT;     /**< Sector Count register */
    Uint8       SECTORNUMBER;    /**< Sector Number register */
    Uint8       CYLINDERLOW;     /**< Cylinder Low register */
    Uint8       CYLINDERHIGH;    /**< Cylinder High register */
    Uint8       DEVICEHEAD;      /**< Device Head register */
    Uint8       COMMAND;         /**< Command register */
} CSL_AtaCommandBlockWrite;

/**
 * @brief       Encapsulation of all readable Command Registers
 *
 * This structure should be instantiated and passed to the
 * CSL_ataReadCommandRegs function, to retrieve the Command Register values
 * from the device.
 */
typedef struct {
    Uint16      DATA;            /**< Data register */
    Uint8       ERROR;           /**< Error register */
    Uint8       SECTORCOUNT;     /**< Sector Count register */
    Uint8       SECTORNUMBER;    /**< Sector Number register */
    Uint8       CYLINDERLOW;     /**< Cylinder Low register */
    Uint8       CYLINDERHIGH;    /**< Cylinder High register */
    Uint8       DEVICEHEAD;      /**< Device Head register */
    Uint8       STATUS;          /**< Status register */
} CSL_AtaCommandBlockRead;

/**
 * @brief       Enumeration of supported command operations
 */
typedef enum {
    CSL_ATA_CMD_PIOENABLE          = 1,  /**< Enable PIO accesses */
    CSL_ATA_CMD_PIODISABLE         = 2,  /**< Disable PIO accesses */

    CSL_ATA_CMD_DMASTARTREAD       = 3,  /**< Initiate DMA read */
    CSL_ATA_CMD_DMASTARTWRITE      = 4,  /**< Initiate DMA write */
    CSL_ATA_CMD_DMASTOP            = 5,  /**< Abort DMA transfer */

    CSL_ATA_CMD_UDMASTARTREAD      = 6,  /**< Initiate UDMA read */
    CSL_ATA_CMD_UDMASTARTWRITE     = 7,  /**< Initiate UDMA write */
    CSL_ATA_CMD_UDMASTOP           = 8,  /**< Abort UDMA transfer */

    CSL_ATA_CMD_IORDYTIMEOUTCLEAR  = 9,  /**< Clear the IORDY time-out bit */
    CSL_ATA_CMD_INTRSTATUSCLEAR    = 10, /**< Clear the interrupt status bit */
    CSL_ATA_CMD_DMAERRORCLEAR      = 11, /**< Clear the DMA error bit */

    CSL_ATA_CMD_DMADESCTABLE       = 12, /**< Set DMA Descriptor Table Base */

    CSL_ATA_CMD_UDMA_TIMING_MODE   = 13, /**< Set IODFTM Target UDMA
                                          *   Timing Mode
                                          */
    CSL_ATA_CMD_MISR_ON            = 14, /**< Set MISR ON */
    CSL_ATA_CMD_MISR_OFF           = 15, /**< Set MISR OFF */
    CSL_ATA_CMD_IODFTM_EN_BREAK    = 16, /**< Enable IODFTM Target Device to
                                          *   generate pauses & stops during
                                          *   UDMA transfers
                                          */
    CSL_ATA_CMD_IODFTM_ENABLE      = 17, /**< Enable IODFTM Target module to be
                                          *   selected to respond to the host.
                                          */
    CSL_ATA_CMD_EXTERNAL_ENABLE    = 18, /**< Enable External Target module to
                                          *   selected to respond to the host.
                                          */
    CSL_ATA_CMD_IODFTM_UDMA_ENABLE = 19, /**< Enable the IODFTM Target module
                                          * to support UDMA mode
                                          */
    CSL_ATA_CMD_IODFTM_PIO_ENABLE  = 20, /**< Enable the IODFTM Target module
                                          * to support PIO & Multi-Word mode
                                          */
    CSL_ATA_CMD_MMS_OUT            = 21, /**< Select the core outputs for
                                          *   capture
                                          */
    CSL_ATA_CMD_MMS_IN             = 22, /**< Select the core inputs for capture
                                          */
    CSL_ATA_CMD_TEST_ENABLE        = 23, /**< Selects the Test Mode */
    CSL_ATA_CMD_NORMAL_ENABLE      = 24, /**< Selects the Normal
                                          *   Functional Mode
                                          */
    CSL_ATA_CMD_TEST_OP_ENABLE     = 25, /**< Enable Test Output */
    CSL_ATA_CMD_TEST_OP_DISABLE    = 26, /**< Disable Test Output */
    CSL_ATA_CMD_SET_MISR_STATE     = 27  /**< Set the MISR state */
} CSL_AtaHwControlCmd;

/**
 * @brief       Enumeration of supported queries
 */
typedef enum {
    CSL_ATA_QUERY_CABLEID       = 1,  /**< Primary, Secondary: 80, 40 */

    CSL_ATA_QUERY_DMACAPABILITY = 2,  /**< ENABLED, DISABLED */

    CSL_ATA_QUERY_IORDYTIMEOUT  = 3,  /**< IORDY Timeout functionality status */
    CSL_ATA_QUERY_INTSTATUS     = 4,  /**< IDE Interrupt status */
    CSL_ATA_QUERY_DMAERROR      = 5,  /**< DMA Error status */
    CSL_ATA_QUERY_IDEACTIVE     = 6,  /**< IDE Active status */
    CSL_ATA_QUERY_RXCOUNT       = 7,  /**< No of bytes received from a device
                                       *   during a PRD transaction
                                       */
    CSL_ATA_QUERY_TXCOUNT       = 8,  /**< No of bytes transmitted to a device
                                       *   during a PRD transaction
                                       */
    CSL_ATA_QUERY_DMARQ         = 9,  /**< Status of DMARQ signal */
    CSL_ATA_QUERY_INTRQ         = 10, /**< Status of INTRQ signal */
    CSL_ATA_QUERY_DMACKN        = 11, /**< Status of DMACKN signal */
    CSL_ATA_QUERY_TLEC          = 12, /**< The number of cycles MISR count will
                                       *   be accumulated in IODFT Test Logic
                                       *   Execution Counter Register
                                       */
    CSL_ATA_QUERY_MISR          = 13  /**< The MISR result signature of a given
                                       *   test after the download function
                                       *   is executed
                                       */
} CSL_AtaHwStatusQuery;

/** @brief IODFT MISR structure
*
* This structure holds the three IODFT MISR Registers - TLMR, TLMR2 & TLMR3
*/
typedef struct {
    Uint32 misr;   /**< MISR value */