csl_uart.h

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */

/** @mainpage UART CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for
 * the UART module across various devices. The CSL developer is expected to
 * refer to this document while designing APIs for these modules. Some of the
 * listed APIs may not be applicable to a given UART module. While other cases
 * this list of APIs may not be sufficient to cover all the features of a
 * particular UART Module. The CSL developer should use his discretion designing
 * new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02
 *
 */

/** Modification 1
 *  @file  csl_uart.h
 *  @brief UART functional layer API header file
 *
 *  Path: \\(CSLPATH)\\ipmodules\\uart\\src
 *
 *  @internal
 *  @date 30th April, 2004
 *  @author Pratheesh Gangadhar ([e-mail])
 */
/* =============================================================================
 *  Revision History
 *  ===============
 *
 *  07-Sep-2004 brn Updated for the new CSL architecture
 *  11-Oct-2004 brn Updated with the code review comments.
 * =============================================================================
*/

#ifndef _CSL_UART_H_
#define _CSL_UART_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>
#include <csl_error.h>
#include <csl_types.h>
#include <cslr_uart.h>
#include <soc.h>

/**
 *  @defgroup CSL_UART_API UART
 *  @internal Based on <b>Catalog DSP UART Peripheral Module Design
 *  Requirement/Specification Rev 0.7
 */

/**
 *  @defgroup CSL_UART_DATASTRUCT Data Structures
 *  @ingroup CSL_UART_API
 */

/**
 *  @defgroup CSL_UART_DEFINE  Defines
 *  @ingroup CSL_UART_API
 */

/**
 *  @defgroup CSL_UART_ENUM  Enumerated Data Types
 *  @ingroup CSL_UART_API
 */

/**
 *  @defgroup CSL_UART_FUNCTION  Functions
 *  @ingroup CSL_UART_API
 */


/**************************************************************************\
* UART global macro declarations
\**************************************************************************/

/**
 *  @defgroup CSL_UART_PARITY_DEFINE Parity Controls
 *  @ingroup CSL_UART_DEFINE
 *
 *
 */

/* Definitions for default hardware setup start */
/** Default clock frequency */
#define CSL_UART_CLK_FREQ            (0x24000000)

/** Enable all Interrupts */
#define CSL_UART_INTR_ENALL          (0x15)

/* End of definitions for default hardware setup */

/** Disable parity generation and detection */
#define CSL_UART_PARITY_DISABLE      (CSL_FMK(UART_LCR_PEN, 0) >> 3)

/** Enable parity generation and detection */
#define CSL_UART_PARITY_ENABLE       (CSL_FMK(UART_LCR_PEN, 1) >> 3)

/** Enable odd parity generation and detection, if PARITY is enabled */
#define CSL_UART_PARITY_ODD          (CSL_FMK(UART_LCR_EPS, 0) >> 3)

/** Enable even parity generation and detection, if PARITY is enabled */
#define CSL_UART_PARITY_EVEN         (CSL_FMK(UART_LCR_EPS, 1) >> 3)

/** Disable stick parity */
#define CSL_UART_STICKPARITY_DISABLE (CSL_FMK(UART_LCR_SP, 0) >> 3)

/** When stick parity is enabled and even parity is selected, the parity bit
 *  is transmitted and checked as cleared
 *  @n When stick parity is enabled and odd parity is selected, the parity bit is
 *   transmitted and checked as set
 */

#define CSL_UART_STICKPARITY_ENABLE  (CSL_FMK(UART_LCR_SP, 1) >> 3)

/**
 *  @defgroup CSL_UART_INTRSTAT_DEFINE Interrupt Enable Masks
 *  @ingroup CSL_UART_DEFINE
 *
 * @{
 */

/** Enable modem status interrupt */
#define CSL_UART_INTR_MODEMSTAT       CSL_FMK(UART_IER_EDSSI, 1)

/** Enable receiver line status interrupt */
#define CSL_UART_INTR_RXLINESTAT      CSL_FMK(UART_IER_ELSI, 1)

/** Enable THR empty interrupt */
#define CSL_UART_INTR_THR_EMPTY       CSL_FMK(UART_IER_ETBEI, 1)

/** Enable receive data available and character timeout indication interrupt*/
#define CSL_UART_INTR_RDA_CTI         CSL_FMK(UART_IER_ERBI, 1)

/**
 *  @defgroup CSL_UART_LINESTAT_DEFINE Line Status Masks
 *  @ingroup CSL_UART_DEFINE
 *
 *
 */

/** This bit is set whenever a complete incoming character has been received
 *  and transferred into the RBR or the FIFO
 */
#define CSL_UART_LINESTAT_DATAREADY      CSL_FMK(UART_LSR_DR, 1)

/** This bit is set whenever a character is written to the RBR before
 *  the previous character was read by the CPU, in so doing the
 *  previous character is lost
 */
#define CSL_UART_LINESTAT_OVERRUN_ERR    CSL_FMK(UART_LSR_OE, 1)

/** This bit is set whenever the parity of the receive data character
 *  does not match the parity selected in the LCR[4]
 */
#define CSL_UART_LINESTAT_PARITY_ERR     CSL_FMK(UART_LSR_PE, 1)

/** This bit is set whenever the receive data character does not have
 *  a valid stop bit
 */
#define CSL_UART_LINESTAT_FRAME_ERR      CSL_FMK(UART_LSR_FE, 1)

/** This bit is set whenever the receive data input was held low for
 *  longer than a full-word transmission time
 */
#define CSL_UART_LINESTAT_BREAKINDI      CSL_FMK(UART_LSR_BI, 1)

/** This bit is set whenever the THR is empty, indicating that the UART
 *  is ready to accept a new character
 */
#define CSL_UART_LINESTAT_THR_EMPTY      CSL_FMK(UART_LSR_THRE, 1)

/**  This bit is set when both the THR and the TSR are empty */
#define CSL_UART_LINESTAT_TXEMPTY        CSL_FMK(UART_LSR_TEMT, 1)

/** In the non-FIFO mode, this bit is set when there is a parity error,
 *  framing error, or break indicator in the receiver buffer register (RBR)
 */
#define CSL_UART_LINESTAT_RXFIFO_ERR     CSL_FMK(UART_LSR_RXFIFOE, 1)

/**
 *  @defgroup CSL_UART_MODEMSTAT_DEFINE Modem Status Masks
 *  @ingroup CSL_UART_DEFINE
 *
 *
 */

/** Indicates that the CTS input has changed state
 *  since the last time it was read by the CPU
 */
#define CSL_UART_MODEMSTAT_CTS    CSL_FMK(UART_MSR_DCTS, 1)

/** Indicates that the DSR input has changed state
 *  since the last time it was read by the CPU
 */
#define CSL_UART_MODEMSTAT_DSR    CSL_FMK(UART_MSR_DDSR, 1)

/** Indicates that the RI input has changed from a low to a high */
#define CSL_UART_MODEMSTAT_RI     CSL_FMK(UART_MSR_TERI, 1)

/** Indicates that the DCD input has changed state
 *  since the last time it was read by the CPU
 */
#define CSL_UART_MODEMSTAT_DCD    CSL_FMK(UART_MSR_DDCD, 1)

/*TODO Need to change abbreviation in register layer*/

/** The complement of the CTS input*/
#define CSL_UART_MODEMSTAT_NCTS   CSL_FMK(UART_MSR_CTS, 1)

/** The complement of the DSR input*/
#define CSL_UART_MODEMSTAT_NDSR   CSL_FMK(UART_MSR_DSR, 1)

/** The complement of the RI input*/
#define CSL_UART_LINESTAT_NRI     CSL_FMK(UART_MSR_RI, 1)

/** The complement of the DCD input*/
#define CSL_UART_LINESTAT_NDCD    CSL_FMK(UART_MSR_DCD, 1)


/**
 *  @defgroup CSL_UART_BAUDRATE_DEFINE Baud Rate
 *  @ingroup CSL_UART_DEFINE
 *
 */
/** 2.4Kb/s*/
#define CSL_UART_BAUD_2_4K        2400

/** 4.8 Kb/s */
#define CSL_UART_BAUD_4_8K        4800

/** 9.6 Kb/s   */
#define CSL_UART_BAUD_9_6K        9600

/**14.4 Kb/s */
#define CSL_UART_BAUD_14_4K      14400

/**19.2 Kb/s */
#define CSL_UART_BAUD_19_2K      19200

/**28.8 Kb/s */
#define CSL_UART_BAUD_28_8K      28800

/** 38.4 Kb/s*/
#define CSL_UART_BAUD_38_4K      38400

/**57.6 Kb/s */
#define CSL_UART_BAUD_57_6K      57600

/**115.2 Kb/s */
#define CSL_UART_BAUD_115_2K    115200

/**
@} */


/**************************************************************************\
* UART global typedef declarations
\**************************************************************************/

/**
 *  @defgroup CSL_UART_NUMSTOPBIT_ENUM Number of Stop Bits
 *  @ingroup CSL_UART_ENUM
 *
 @{
 */
/**
 *  @brief  Enums for the Number of Stop bits
 *   This is used by control commands to set the number of stop bits
 */
typedef enum {
    /**   Number of Stop bits = 1 */
    CSL_UART_NUMSTOP_1      = 0,

    /**  Number of Stop bits = 1.5
     *        (when character length equal to 5) or 2
     *         (when character length equal to 6,7 or 8)
     */
    CSL_UART_NUMSTOP_1_5or2 = 1

} CSL_UartNumStop;

/**
@} */

/**
 *  @defgroup CSL_UART_DMACTRL_ENUM DMA Control
 *  @ingroup CSL_UART_ENUM
 *
 @{
 */
/**
 *  @brief  Enums for DMA configuration
 *  This is used by control commands to configure DMA mode
 */
typedef enum {
    /**   Disable DMA */
    CSL_UART_DMA_DISABLE = CSL_UART_FCR_DMAMODE1_DISABLE,

    /**  Enable DMA MODE1 */
    CSL_UART_DMA_ENABLE = CSL_UART_FCR_DMAMODE1_ENABLE

} CSL_UartDmaCtrl;


/**
 *  @defgroup CSL_UART_EMUMODE_ENUM Emulation Control
 *  @ingroup CSL_UART_ENUM
 *
 */
/**
 *  @brief  Enums for Emulation modes
 *  This is used by control commands to configure emulation mode
 */
typedef enum {
    /**  UART stops immediately */
    CSL_UART_EMU_STOP = CSL_UART_PWREMU_MGMT_FREE_STOP,

    /**  UART runs free */
    CSL_UART_EMU_RUN  = CSL_UART_PWREMU_MGMT_FREE_RUN

} CSL_UartEmuCtrl;
/**
@} */

/**
 *  @defgroup CSL_UART_RSTCTRL_ENUM Reset Control
 *  @ingroup CSL_UART_ENUM
 *
 @{
 */
/**
 *  @brief  Enums for Reset control
 *  This is used by control commands to reset/enable UART
 */
typedef enum {
    /**< <b>: Resets UART</b>*/
    CSL_UART_RESET = CSL_UART_PWREMU_MGMT_URST_RESET,

    /**< <b>: Re-enables transmitter and receiver</b>*/
    CSL_UART_ENABLE = CSL_UART_PWREMU_MGMT_URST_ENABLE

} CSL_UartResetCtrl;
/**
@} */


/**
 * @defgroup CSL_UART_LOOPCTRL_ENUM Loop Control
 *  @ingroup CSL_UART_ENUM
 *
 @{
 */
/**
 *  @brief  Enums for Loopback mode control
 *  This is used by control commands to enable/disable loopback mode
 */
typedef enum {
    /**< <b>: Normal mode of operation</b>*/
    CSL_UART_LOOP_DISABLE = CSL_UART_MCR_LOOP_DISABLE,

    /**< <b>: Enables loopback mode</b>*/
    CSL_UART_LOOP_ENABLE  = CSL_UART_MCR_LOOP_ENABLE

} CSL_UartLoopCtrl;
/**
@} */

/**
 *  @defgroup CSL_UART_FIFOCTRL_ENUM Fifo Control
 *  @ingroup CSL_UART_ENUM
 *
 @{
 */

/**
 *  @brief  Enums for Fifo configuration
 *  This is used by control commands to enable/disable FIFO
 */
typedef enum {
    /**< <b>:Disables FIFO mode</b>*/
    CSL_UART_FIFO_DISABLE = CSL_UART_FCR_FIFOEN_DISABLE,

    /**  Enables FIFO mode*/
    CSL_UART_FIFO_ENABLE  = CSL_UART_FCR_FIFOEN_ENABLE

} CSL_UartFifoCtrl;
/**
@} */

/**
 *  @defgroup CSL_UART_CHARLEN_ENUM Character Length
 *  @ingroup CSL_UART_ENUM
 *
 @{
 */
/**
 *  @brief  Enums for the UART character length
 * This is used by control commands to set the UART character length
 */
typedef enum {
    /** 5 bits */
    CSL_UART_CHARLEN_5    =  CSL_UART_LCR_WLS_BITS5,

    /** 6 bits */
    CSL_UART_CHARLEN_6    =  CSL_UART_LCR_WLS_BITS6,

    /** 7 bits */
    CSL_UART_CHARLEN_7    =  CSL_UART_LCR_WLS_BITS7,

    /** 8 bits  */
    CSL_UART_CHARLEN_8    =  CSL_UART_LCR_WLS_BITS8

} CSL_UartCharLen;
/**
@} */

/**
 *  @defgroup CSL_UART_RXFIFTL_ENUM Receive FIFO Trigger Level
 *  @ingroup CSL_UART_ENUM
 *
 @{
 */

/**
 *  @brief  Enums for the UART receive FIFO trigger level
 * This is used by control commands to set rx FIFO trigger level
 */
typedef enum {
    /**  Character length of 1  */
    CSL_UART_RXTRIGLEVEL_1    =  CSL_UART_FCR_RXFIFTL_CHAR1,

    /** Character length of 4  */
    CSL_UART_RXTRIGLEVEL_4    =  CSL_UART_FCR_RXFIFTL_CHAR4,

    /** Character length of 8 */
    CSL_UART_RXTRIGLEVEL_8    =  CSL_UART_FCR_RXFIFTL_CHAR8,

    /** Character length of 14  */
    CSL_UART_RXTRIGLEVEL_14    =  CSL_UART_FCR_RXFIFTL_CHAR14

} CSL_UartRxFifoTrigLevel;
/**
@} */

/**
 *  @defgroup CSL_UART_AUTOFLOW_ENUM Autoflow Controls
 *  @ingroup CSL_UART_ENUM
 *
 @{
 */

/**
 *  @brief  Enums for the UART autoflow configuration
 * This is used for configuring autoflow settings
 */
typedef enum {
    /** Auto-rts and auto-cts disabled  */
    CSL_UART_AUTOFLOW_DISABLE = 0,

    /** Auto-cts only enabled  */
    CSL_UART_AUTO_CTS         = 1,

    /** Auto-rts and auto-cts enabled  */
    CSL_UART_AUTO_CTS_RTS     = 2

} CSL_UartAutoflowCtrl;
/**
@} */

/**
 *  @defgroup CSL_UART_INTRSOURCE_ENUM Interrupt Source
 *  @ingroup CSL_UART_ENUM
 *
 @{
 */
/**
 *  @brief  Enums for the Interrupt Source
 *  This is used for query Interrupt Source.
 */
typedef enum {
    /** No Interrupt Occured*/
    CSL_UART_INTRSOURCE_NONE        =  CSL_UART_IIR_IPEND_NONE,

    /** Modem status interrupt*/
    CSL_UART_INTRSOURCE_MODEMSTAT   =  CSL_UART_IIR_INTID_MODSTAT << 1,

    /** THR empty interrupt*/
    CSL_UART_INTRSOURCE_THRE        =  CSL_UART_IIR_INTID_THRE << 1,

    /** Rx  data available interrupt*/
    CSL_UART_INTRSOURCE_RDA         =  CSL_UART_IIR_INTID_RDA << 1,

    /**  Rx line status interrupt*/
    CSL_UART_INTRSOURCE_RXLINESTAT  =  CSL_UART_IIR_INTID_RLS << 1 ,

    /** Character timeout indication interrupt*/
    CSL_UART_INTRSOURCE_CHARTIMEOUT =  CSL_UART_IIR_INTID_CTI << 1

} CSL_UartIntrSource;
/**
@} */