csl_vlynqaux.h

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/**
 *   @file  csl_vlynqAux.h
 *
 *   @path $(CSLPATH)\vlynq\v1\src
 *
 *   @brief  VLYNQ CSL implementation on ARM side
 *
 */

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/* =============================================================================
 *  Revision History
 *  ===============
 *  20-Dec-2004 Nsr File Created from CSL_vlynqHwControl.c and
 *                  CSL_vlynqGetHwStatus.c
 *
 * =============================================================================
 */
#ifndef _CSL_VLYNQAUX_H_
#define _CSL_VLYNQAUX_H_

#include <csl_vlynq.h>

#ifdef __cplusplus
extern "C" {
#endif

/* Control commands */

/** ============================================================================
 *   @n@b CSL_vlynqPmenConfigure
 *
 *   @b Description
 *   @n Configure the value of the Power Management Control bit.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq       Handle to the VLYNQ instance

        powerEnVal   value to be configured
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The Power Management Control bit is configured with the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqPmenConfigure (hVlynq, 0x01);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_vlynqPmenConfigure (
    CSL_VlynqHandle  hVlynq,
    Uint32           powerEnVal
)
{
    /* Configure the Power Management enable/disable bit */
    CSL_FINS(hVlynq->regs->CTRL, VLYNQ_CTRL_PMEN, powerEnVal);
    return;
}


/** ============================================================================
 *   @n@b CSL_vlynqSclkpudisConfigure
 *
 *   @b Description
 *   @n Configure the value of the Serial Clock Pull-up Control bit.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq       Handle to the VLYNQ instance

        sclkpudis    value to be configured
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The Serial Clock Pull-up Control bit is configured with the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqSclkpudisConfigure (hVlynq, 0x01);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_vlynqSclkpudisConfigure (
    CSL_VlynqHandle  hVlynq,
    Uint32           sclkpudis
)
{
    /* Configure the Serial Clock Pull-up enable/disable bit */
    CSL_FINS(hVlynq->regs->CTRL, VLYNQ_CTRL_SCLKXPUDIS, sclkpudis);
    return;
}


/** ============================================================================
 *   @n@b CSL_vlynqSetRxSampleVal
 *
 *   @b Description
 *   @n Set the RTM sample value.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq         Handle to the VLYNQ instance

        rxSampleVal    RTM sample value to be configured.
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The RTM sample value is set to the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqSetRxSampleVal (hVlynq, rxSampleVal );
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_vlynqSetRxSampleVal (
    CSL_VlynqHandle          hVlynq,
    CSL_VlynqRtmSampleVal    rxSampleVal
)
{
    Uint32 temp;
    /* Set RTM sample value for simultaneous write to rxsampleval and rtmvaliwr
       fields */
    temp = hVlynq->regs->CTRL;
    CSL_FINS(temp, VLYNQ_CTRL_RXSAMPELVAL, rxSampleVal);
    CSL_FINS(temp, VLYNQ_CTRL_RTMVALIDWR, 1);
    hVlynq->regs->CTRL = temp;

    return;
}


/** ============================================================================
 *   @n@b CSL_vlynqRtmValidWrConfigure
 *
 *   @b Description
 *   @n Configure the value of the RTM write valid bit.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq       Handle to the VLYNQ instance

        wrValid      value to be configured
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The RTM write valid bit is configured with the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqRtmValidWrConfigure (hVlynq, wrValid);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_vlynqRtmValidWrConfigure (
    CSL_VlynqHandle  hVlynq,
    Uint32           wrValid
)
{
    /** Enable RTM Write valid -odd:7*/
    CSL_FINS(hVlynq->regs->CTRL, VLYNQ_CTRL_RTMVALIDWR, wrValid);
    return;
}


/** ============================================================================
 *   @n@b CSL_vlynqRtmConfigure
 *
 *   @b Description
 *   @n Configure the value of the RTM Enable/Disable bit.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq       Handle to the VLYNQ instance

        rtmEnval     value to be configured
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The RTM Enable/Disable bit is configured with the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqRtmConfigure (hVlynq, rtmEnval);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_vlynqRtmConfigure (
    CSL_VlynqHandle  hVlynq,
    Uint32           rtmEnval
)
{
    /** setup the Enable/Disable bit of  RTM (Receive Timing Manager) */
    CSL_FINS(hVlynq->regs->CTRL, VLYNQ_CTRL_RTMENABLE, rtmEnval);
    return;
}


/** ============================================================================
 *   @n@b CSL_vlynqTxFastPathConfigure
 *
 *   @b Description
 *   @n Configure the value of the Transmit Fast Path bit.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq       Handle to the VLYNQ instance

        txFastPath   value to be configured
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The Transmit Fast Path bit is configured with the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqTxFastPathConfigure (hVlynq, txFastPath);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_vlynqTxFastPathConfigure (
    CSL_VlynqHandle  hVlynq,
    Uint32           txFastPath
)
{
    /** Selects TX fast path */
    CSL_FINS(hVlynq->regs->CTRL, VLYNQ_CTRL_TXFASTPATH, txFastPath);
    return;
}


/** ============================================================================
 *   @n@b CSL_vlynqClkDivSet
 *
 *   @b Description
 *   @n Set the clock divisor.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq       Handle to the VLYNQ instance

        clkDiv       Clock divisor value to be configured.
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The clock divisor is set to the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqClkDivSet (hVlynq, CSL_VLYNQ_CLKDIV_1 );
        ...
     @endverbatim
 * ===========================================================================
 */

CSL_IDEF_INLINE
void CSL_vlynqClkDivSet (
    CSL_VlynqHandle  hVlynq,
    CSL_VlynqSclkDiv clkDiv
)
{
    /* Set the clock divisor */
    CSL_FINS(hVlynq->regs->CTRL, VLYNQ_CTRL_CLKDIV, clkDiv);

    return;
}

/** ============================================================================
 *   @n@b CSL_vlynqClkDirSet
 *
 *   @b Description
 *   @n Set the clock direction.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq       Handle to the VLYNQ instance

        clkDir       Clock direction to be configured
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The clock direction is set to the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqClkDirSet (hVlynq, 0x01);
        ...
     @endverbatim
 * ===========================================================================
 */

CSL_IDEF_INLINE
void CSL_vlynqClkDirSet (
    CSL_VlynqHandle      hVlynq,
    CSL_VlynqClkDir      clkDir
)
{
    /* Set the clock direction */
    CSL_FINS(hVlynq->regs->CTRL, VLYNQ_CTRL_CLKDIR, clkDir);

    return;
}

/** ============================================================================
 *   @n@b CSL_vlynqIntLocalConfigure
 *
 *   @b Description
 *   @n Configure the value of the INTLOC bit.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq            Handle to the VLYNQ instance

        intLocalVal       value to be configured
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The INTLOC bit is configured with the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqIntLocalConfigure (hVlynq, 0x01);
        ...
     @endverbatim
 * ===========================================================================
 */

CSL_IDEF_INLINE
void CSL_vlynqIntLocalConfigure (
    CSL_VlynqHandle  hVlynq,
    Uint32           intLocalVal
)
{
    /* Configure the interrupt local bit */
    CSL_FINS(hVlynq->regs->CTRL, VLYNQ_CTRL_INTLOCAL, intLocalVal);

    return;
}

/** ============================================================================
 *   @n@b CSL_vlynqIntEnConfigure
 *
 *   @b Description
 *   @n Configure the value of the INTENABLE bit.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq       Handle to the VLYNQ instance

        intEnVal     value to be configured
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The INTENABLE bit is configured with the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqIntEnConfigure (hVlynq, 0x01);
        ...
     @endverbatim
 * ===========================================================================
 */

CSL_IDEF_INLINE
void CSL_vlynqIntEnConfigure (
    CSL_VlynqHandle  hVlynq,
    Uint32           intEnVal
)
{
    /* Configure the interrupt enable bit */
    CSL_FINS (hVlynq->regs->CTRL, VLYNQ_CTRL_INTENABLE, intEnVal);

    return;
}

/** ============================================================================
 *   @n@b CSL_vlynqIntVecConfigure
 *
 *   @b Description
 *   @n Configure the value of the INTVEC bits.
 *
 *   @b Arguments
 *   @verbatim
        hVlynq       Handle to the VLYNQ instance

        intVecVal    value to be configured
     @endverbatim
 *
 *   <b> Return Value </b>
 *       None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The INTVEC bits is configured with the value passed.
 *
 *   @b Modifies
 *   @n VLYNQ control register.
 *
 *   @b Example
 *   @verbatim
        CSL_VlynqHandle     hVlynq;
         ...
        CSL_vlynqIntVecConfigure (hVlynq, CSL_VLYNQ_INT_VECTOR_2);
        ...
     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_vlynqIntVecConfigure (
    CSL_VlynqHandle        hVlynq,
    CSL_VlynqIntVector     intVecVal
)
{
    /* Configure the interrupt vector bits */
    CSL_FINS(hVlynq->regs->CTRL, VLYNQ_CTRL_INTVEC, intVecVal);
    return;
}


/** ============================================================================
 *   @n@b CSL_vlynqIntVecClear
 *