📄 cslr_tmr.h
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#define CSL_TMR_GPTDAT_GPDIR_GPIO_DATI12_RESETVAL (0x00000000u)/*----GPIO_DATI12 Tokens----*/#define CSL_TMR_GPTDAT_GPDIR_GPIO_DATI12_DISABLE (0x00000000u)#define CSL_TMR_GPTDAT_GPDIR_GPIO_DATI12_ENABLE (0x00000001u)#define CSL_TMR_GPTDAT_GPDIR_RESETVAL (0x00000000u)/* TIM12 */#define CSL_TMR_TIM12_CNT12_MASK (0xFFFFFFFFu)#define CSL_TMR_TIM12_CNT12_SHIFT (0x00000000u)#define CSL_TMR_TIM12_CNT12_RESETVAL (0x00000000u)#define CSL_TMR_TIM12_RESETVAL (0x00000000u)/* TIM34 */#define CSL_TMR_TIM34_CNT34_MASK (0xFFFFFFFFu)#define CSL_TMR_TIM34_CNT34_SHIFT (0x00000000u)#define CSL_TMR_TIM34_CNT34_RESETVAL (0x00000000u)#define CSL_TMR_TIM34_RESETVAL (0x00000000u)/* PRD12 */#define CSL_TMR_PRD12_PRD12_MASK (0xFFFFFFFFu)#define CSL_TMR_PRD12_PRD12_SHIFT (0x00000000u)#define CSL_TMR_PRD12_PRD12_RESETVAL (0x00000000u)#define CSL_TMR_PRD12_RESETVAL (0x00000000u)/* PRD34 */#define CSL_TMR_PRD34_PRD34_MASK (0xFFFFFFFFu)#define CSL_TMR_PRD34_PRD34_SHIFT (0x00000000u)#define CSL_TMR_PRD34_PRD34_RESETVAL (0x00000000u)#define CSL_TMR_PRD34_RESETVAL (0x00000000u)/* TCR */#define CSL_TMR_TCR_TIEN34_MASK (0x02000000u)#define CSL_TMR_TCR_TIEN34_SHIFT (0x00000019u)#define CSL_TMR_TCR_TIEN34_RESETVAL (0x00000000u)/*----TIEN34 Tokens----*/#define CSL_TMR_TCR_TIEN34_NOT_GATED (0x00000000u)#define CSL_TMR_TCR_TIEN34_GATED_BY_TINP (0x00000001u)#define CSL_TMR_TCR_CLKSRC34_MASK (0x01000000u)#define CSL_TMR_TCR_CLKSRC34_SHIFT (0x00000018u)#define CSL_TMR_TCR_CLKSRC34_RESETVAL (0x00000000u)/*----CLKSRC34 Tokens----*/#define CSL_TMR_TCR_CLKSRC34_VBUS (0x00000000u)#define CSL_TMR_TCR_CLKSRC34_INPUT_PIN (0x00000001u)#define CSL_TMR_TCR_ENAMODE34_MASK (0x00C00000u)#define CSL_TMR_TCR_ENAMODE34_SHIFT (0x00000016u)#define CSL_TMR_TCR_ENAMODE34_RESETVAL (0x00000000u)/*----ENAMODE34 Tokens----*/#define CSL_TMR_TCR_ENAMODE34_DISABLED (0x00000000u)#define CSL_TMR_TCR_ENAMODE34_ONCE (0x00000001u)#define CSL_TMR_TCR_ENAMODE34_CONTINUOUS (0x0000000Au)#define CSL_TMR_TCR_PWID34_MASK (0x00300000u)#define CSL_TMR_TCR_PWID34_SHIFT (0x00000014u)#define CSL_TMR_TCR_PWID34_RESETVAL (0x00000000u)/*----PWID34 Tokens----*/#define CSL_TMR_TCR_PWID34_INACTIVE_1CYCLE (0x00000000u)#define CSL_TMR_TCR_PWID34_INACTIVE_2CYCLES (0x00000001u)#define CSL_TMR_TCR_PWID34_INACTIVE_3CYCLES (0x0000000Au)#define CSL_TMR_TCR_PWID34_INACTIVE_4CYCLES (0x0000000Bu)#define CSL_TMR_TCR_CP34_MASK (0x00080000u)#define CSL_TMR_TCR_CP34_SHIFT (0x00000013u)#define CSL_TMR_TCR_CP34_RESETVAL (0x00000000u)/*----CP34 Tokens----*/#define CSL_TMR_TCR_CP34_PULSE_MODE (0x00000000u)#define CSL_TMR_TCR_CP34_CLOCK_MODE (0x00000001u)#define CSL_TMR_TCR_INVINP34_MASK (0x00040000u)#define CSL_TMR_TCR_INVINP34_SHIFT (0x00000012u)#define CSL_TMR_TCR_INVINP34_RESETVAL (0x00000000u)/*----INVINP34 Tokens----*/#define CSL_TMR_TCR_INVINP34_DONT_INVERT_OUTPUT (0x00000000u)#define CSL_TMR_TCR_INVINP34_INVERT_OUTPUT (0x00000001u)#define CSL_TMR_TCR_INVOUTP34_MASK (0x00020000u)#define CSL_TMR_TCR_INVOUTP34_SHIFT (0x00000011u)#define CSL_TMR_TCR_INVOUTP34_RESETVAL (0x00000000u)/*----INVOUTP34 Tokens----*/#define CSL_TMR_TCR_INVOUTP34_DONT_INVERT_OUTPUT (0x00000000u)#define CSL_TMR_TCR_INVOUTP34_INVERT_OUTPUT (0x00000001u)#define CSL_TMR_TCR_TSTAT34_MASK (0x00010000u)#define CSL_TMR_TCR_TSTAT34_SHIFT (0x00000010u)#define CSL_TMR_TCR_TSTAT34_RESETVAL (0x00000000u)/*----TSTAT34 Tokens----*/#define CSL_TMR_TCR_TSTAT34_LOW (0x00000000u)#define CSL_TMR_TCR_TSTAT34_HIGH (0x00000001u)#define CSL_TMR_TCR_TIEN12_MASK (0x00000200u)#define CSL_TMR_TCR_TIEN12_SHIFT (0x00000009u)#define CSL_TMR_TCR_TIEN12_RESETVAL (0x00000000u)/*----TIEN12 Tokens----*/#define CSL_TMR_TCR_TIEN12_NOT_GATED (0x00000000u)#define CSL_TMR_TCR_TIEN12_GATED_BY_TINP (0x00000001u)#define CSL_TMR_TCR_CLKSRC12_MASK (0x00000100u)#define CSL_TMR_TCR_CLKSRC12_SHIFT (0x00000008u)#define CSL_TMR_TCR_CLKSRC12_RESETVAL (0x00000000u)/*----CLKSRC12 Tokens----*/#define CSL_TMR_TCR_CLKSRC12_VBUS (0x00000000u)#define CSL_TMR_TCR_CLKSRC12_INPUT_PIN (0x00000001u)#define CSL_TMR_TCR_ENAMODE12_MASK (0x000000C0u)#define CSL_TMR_TCR_ENAMODE12_SHIFT (0x00000006u)#define CSL_TMR_TCR_ENAMODE12_RESETVAL (0x00000000u)/*----ENAMODE12 Tokens----*/#define CSL_TMR_TCR_ENAMODE12_DISABLED (0x00000000u)#define CSL_TMR_TCR_ENAMODE12_ONCE (0x00000001u)#define CSL_TMR_TCR_ENAMODE12_CONTINUOUS (0x0000000Au)#define CSL_TMR_TCR_PWID12_MASK (0x00000030u)#define CSL_TMR_TCR_PWID12_SHIFT (0x00000004u)#define CSL_TMR_TCR_PWID12_RESETVAL (0x00000000u)/*----PWID12 Tokens----*/#define CSL_TMR_TCR_PWID12_INACTIVE_1CYCLE (0x00000000u)#define CSL_TMR_TCR_PWID12_INACTIVE_2CYCLES (0x00000001u)#define CSL_TMR_TCR_PWID12_INACTIVE_3CYCLES (0x0000000Au)#define CSL_TMR_TCR_PWID12_INACTIVE_4CYCLES (0x0000000Bu)#define CSL_TMR_TCR_CP12_MASK (0x00000008u)#define CSL_TMR_TCR_CP12_SHIFT (0x00000003u)#define CSL_TMR_TCR_CP12_RESETVAL (0x00000000u)/*----CP12 Tokens----*/#define CSL_TMR_TCR_CP12_PULSE_MODE (0x00000000u)#define CSL_TMR_TCR_CP12_CLOCK_MODE (0x00000001u)#define CSL_TMR_TCR_INVINP12_MASK (0x00000004u)#define CSL_TMR_TCR_INVINP12_SHIFT (0x00000002u)#define CSL_TMR_TCR_INVINP12_RESETVAL (0x00000000u)/*----INVINP12 Tokens----*/#define CSL_TMR_TCR_INVINP12_DONT_INVERT_OUTPUT (0x00000000u)#define CSL_TMR_TCR_INVINP12_INVERT_OUTPUT (0x00000001u)#define CSL_TMR_TCR_INVOUTP12_MASK (0x00000002u)#define CSL_TMR_TCR_INVOUTP12_SHIFT (0x00000001u)#define CSL_TMR_TCR_INVOUTP12_RESETVAL (0x00000000u)/*----INVOUTP12 Tokens----*/#define CSL_TMR_TCR_INVOUTP12_DONT_INVERT_OUTPUT (0x00000000u)#define CSL_TMR_TCR_INVOUTP12_INVERT_OUTPUT (0x00000001u)#define CSL_TMR_TCR_TSTAT12_MASK (0x00000001u)#define CSL_TMR_TCR_TSTAT12_SHIFT (0x00000000u)#define CSL_TMR_TCR_TSTAT12_RESETVAL (0x00000000u)/*----TSTAT12 Tokens----*/#define CSL_TMR_TCR_TSTAT12_LOW (0x00000000u)#define CSL_TMR_TCR_TSTAT12_HIGH (0x00000001u)#define CSL_TMR_TCR_RESETVAL (0x00000000u)/* TGCR */#define CSL_TMR_TGCR_TDDR34_MASK (0x0000F000u)#define CSL_TMR_TGCR_TDDR34_SHIFT (0x0000000Cu)#define CSL_TMR_TGCR_TDDR34_RESETVAL (0x00000000u)#define CSL_TMR_TGCR_PSC34_MASK (0x00000F00u)#define CSL_TMR_TGCR_PSC34_SHIFT (0x00000008u)#define CSL_TMR_TGCR_PSC34_RESETVAL (0x00000000u)#define CSL_TMR_TGCR_TIMMODE_MASK (0x0000000Cu)#define CSL_TMR_TGCR_TIMMODE_SHIFT (0x00000002u)#define CSL_TMR_TGCR_TIMMODE_RESETVAL (0x00000000u)/*----TIMMODE Tokens----*/#define CSL_TMR_TGCR_TIMMODE_64BIT_GPTIM (0x00000000u)#define CSL_TMR_TGCR_TIMMODE_32BIT_DUAL (0x00000001u)#define CSL_TMR_TGCR_TIMMODE_64BIT_WDTIM (0x0000000Au)#define CSL_TMR_TGCR_TIMMODE_32BIT_CHAINED (0x0000000Bu)#define CSL_TMR_TGCR_TIM34RS_MASK (0x00000002u)#define CSL_TMR_TGCR_TIM34RS_SHIFT (0x00000001u)#define CSL_TMR_TGCR_TIM34RS_RESETVAL (0x00000000u)/*----TIM34RS Tokens----*/#define CSL_TMR_TGCR_TIM34RS_IN_RESET (0x00000000u)#define CSL_TMR_TGCR_TIM34RS_NOT_IN_RESET (0x00000001u)#define CSL_TMR_TGCR_TIM12RS_MASK (0x00000001u)#define CSL_TMR_TGCR_TIM12RS_SHIFT (0x00000000u)#define CSL_TMR_TGCR_TIM12RS_RESETVAL (0x00000000u)/*----TIM12RS Tokens----*/#define CSL_TMR_TGCR_TIM12RS_IN_RESET (0x00000000u)#define CSL_TMR_TGCR_TIM12RS_NOT_IN_RESET (0x00000001u)#define CSL_TMR_TGCR_RESETVAL (0x00000000u)/* WDTCR */#define CSL_TMR_WDTCR_WDKEY_MASK (0xFFFF0000u)#define CSL_TMR_WDTCR_WDKEY_SHIFT (0x00000010u)#define CSL_TMR_WDTCR_WDKEY_RESETVAL (0x00000000u)/*----WDKEY Tokens----*/#define CSL_TMR_WDTCR_WDKEY_PREACTIVE (0x0000A5C6u)#define CSL_TMR_WDTCR_WDKEY_ACTIVE (0x0000DA7Eu)#define CSL_TMR_WDTCR_WDFLAG_MASK (0x00008000u)#define CSL_TMR_WDTCR_WDFLAG_SHIFT (0x0000000Fu)#define CSL_TMR_WDTCR_WDFLAG_RESETVAL (0x00000000u)/*----WDFLAG Tokens----*/#define CSL_TMR_WDTCR_WDFLAG_TIMEOUT (0x00000000u)#define CSL_TMR_WDTCR_WDFLAG_NOTIMEOUT (0x00000001u)#define CSL_TMR_WDTCR_WDEN_MASK (0x00004000u)#define CSL_TMR_WDTCR_WDEN_SHIFT (0x0000000Eu)#define CSL_TMR_WDTCR_WDEN_RESETVAL (0x00000000u)/*----WDEN Tokens----*/#define CSL_TMR_WDTCR_WDEN_DISABLE (0x00000000u)#define CSL_TMR_WDTCR_WDEN_ENABLE (0x00000001u)#define CSL_TMR_WDTCR_WDIKEY_MASK (0x00003000u)#define CSL_TMR_WDTCR_WDIKEY_SHIFT (0x0000000Cu)#define CSL_TMR_WDTCR_WDIKEY_RESETVAL (0x00000000u)/*----WDIKEY Tokens----*/#define CSL_TMR_WDTCR_WDIKEY_NO_IDLE (0x00000000u)#define CSL_TMR_WDTCR_WDIKEY_GO_IDLE_START (0x00000001u)#define CSL_TMR_WDTCR_WDIKEY_GO_IDLE (0x0000000Au)#define CSL_TMR_WDTCR_RESETVAL (0x00000000u)#endif⌨️ 快捷键说明
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