csl_nand.h

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */ 

/** @mainpage NAND CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for
 * the NAND module across various devices. The CSL developer is expected to
 * refer to this document while designing APIs for these modules. Some of the  
 * listed APIs may not be applicable to a given NAND module. While other cases
 * this list of APIs may not be sufficient to cover all the features of a
 * particular NAND Module. The CSL developer should use his discretion
 * designing new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02
 *
 */

/** @file csl_nand.h
 *
 * @brief    Header file for functional layer of CSL
 *
 * Description
 *    - The different enumerations, structure definitions
 *      and function declarations
 *
 * PATH \\(CSLPATH)\\ipmodules\\nfc\\src
 *
 * Modification 1
 *    - modified on: 28/6/2004
 *    - reason: Created the sources
 *
 * @date 28th June, 2004
 * @author Santosh Narayanan.
 *
 */

/* ============================================================================
 *  Revision History
 *  ===============
 *  11-Oct-2004 Nsr removed extern keyword before the function declaration.
 *  02-sep-2004 Nsr updated CSL_NandObj and added CSL_NandBaseAddress, 
 *                  CSL_NandParam,CSL_NandContext,  CSL_NandConfig structures.
 *                 - Updated comments for H/W control cmd and status 
 *                   query enums.
 *                 - Added prototypes for CSL_nandGetBaseAdddress and
 *                   CSL_NandHwSetupRaw.
 *                 - Changed prototypes of CSL_nandInit, CSL_nandOpen.
 *                 - Updated respective comments along with that of 
 *                   CSL_nandClose.
 * ============================================================================
 */

#ifndef _CSL_NAND_H_
#define _CSL_NAND_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <soc.h>
#include <cslr.h>
#include <csl_error.h>
//#include <csl_sysData.h>
#include <csl_types.h>
#include <cslr_nand.h>

/**************************************************************************\
* NAND global macro declarations
\**************************************************************************/

/** Constants for passing parameters to the NAND HwSetup function.
 */

/** For de-selecting Strobe mode for Async banks */
#define CSL_NAND_ASYNC_SS_DISABLE                   (0)
/** For selecting Strobe mode for Async banks */
#define CSL_NAND_ASYNC_SS_ENABLE                    (1)
/** For disabling the Extended Wait mode for Async banks */
#define CSL_NAND_ASYNC_EW_DISABLE                   (0)
/** For enabling the Extended Wait mode for Async banks */
#define CSL_NAND_ASYNC_EW_ENABLE                    (1)
/** For disabling NAND FLASH on chip select 5 */
#define CSL_NAND_CS5_NAND_DISABLE                   (0)
/** For enabling NAND FLASH on chip select 5 */
#define CSL_NAND_CS5_NAND_ENABLE                    (1)
/** For disabling NAND FLASH on chip select 4 */
#define CSL_NAND_CS4_NAND_DISABLE                   (0)
/** For enabling NAND FLASH on chip select 4 */
#define CSL_NAND_CS4_NAND_ENABLE                    (1)
/** For disabling NAND FLASH on chip select 3 */
#define CSL_NAND_CS3_NAND_DISABLE                   (0)
/** For enabling NAND FLASH on chip select 3 */
#define CSL_NAND_CS3_NAND_ENABLE                    (1)
/** For disabling NAND FLASH on chip select 2 */
#define CSL_NAND_CS2_NAND_DISABLE                   (0)
/** For enabling NAND FLASH on chip select 2 */
#define CSL_NAND_CS2_NAND_ENABLE                    (1)

/** Asynchronous Wait Cycle Configuration defaults  */
#define CSL_NAND_ASYNCWAITCYCLECONFIG_DEFAULTS   {  \
    (Uint16)1,(Uint16)1,(Uint16)1,(Uint16)1,        \
    (Uint16)0,(Uint16)0,(Uint16)0,(Uint16)0,        \
    (Uint16)0x80 }

/** NAND Asynchronous Bank Configuration defaults  */
#define CSL_NAND_ASYNCBANKCONFIG_DEFAULTS  {    \
    (Uint16)0,    \
    (Uint16)0,    \
    (Uint16)0xF,  \
    (Uint16)0X3F, \
    (Uint16)7,    \
    (Uint16)0XF,  \
    (Uint16)0X3F, \
    (Uint16)7,    \
    (Uint16)3,    \
    (Uint16)1    }

/** NAND Flash Control defaults  */
#define CSL_NAND_NANDFLASHCONTROL_DEFAULTS{  \
    (Uint16)0,      \
    (Uint16)0,      \
    (Uint16)0,      \
    (Uint16)0      }

/**************************************************************************\
* NAND global typedef declarations
\**************************************************************************/

/** @brief This object contains the reference to the instance of NAND opened
 *  using the @a CSL_nandOpen().
 *
 *  The pointer to this, is passed to all NAND CSL APIs.
 */
typedef struct CSL_NandObj {
    /** Base-address of the configuration registers of the peripheral
     */
    CSL_NandRegsOvly regs;
    /** This is the instance of NAND being referred to by this object  */
    CSL_InstNum perNum;
}CSL_NandObj;

/** @brief This will have the base-address information for the peripheral
 *  instance
 */
typedef struct {
    /** Base-address of the Configuration registers of NAND.
     */
    CSL_NandRegsOvly regs;
} CSL_NandBaseAddress;

/** @brief NAND specific parameters. Present implementation doesn't have
 *  any specific parameters.
 */
typedef struct {
    /** Bit mask to be used for module specific parameters.
     *  The below declaration is just a place-holder for future
     *  implementation.
     */
    CSL_BitMask16   flags;
} CSL_NandParam;

/** @brief NAND specific context information. Present implementation doesn't
 *  have any Context information.
 */

typedef struct {
    /** Context information of NAND.
     *  The below declaration is just a place-holder for future
     *  implementation.
     */
    Uint16  contextInfo;
} CSL_NandContext;

/** @brief Config structure of NAND. This is used to configure NAND
     * using CSL_HwSetupRaw function
     */
typedef struct  {
    /** Asynchronous Wait Cycle Configuration Register */
    volatile Uint32 AWCCR;
    /** Asynchronous Bank 1 Configuration Register */
    volatile Uint32 AB1CR;
    /** Asynchronous Bank 2 Configuration Register */
    volatile Uint32 AB2CR;
    /** Asynchronous Bank 3 Configuration Register */
    volatile Uint32 AB3CR;
    /** Asynchronous Bank 4 Configuration Register */
    volatile Uint32 AB4CR;
    /** NAND Interrupt Raw Register */
    volatile Uint32 NIRR;
    /** NAND Interrupt Mask Register */
    volatile Uint32 NIMR;
    /** NAND Interrupt Mask Set Register */
    volatile Uint32 NIMSR;
    /** NAND Interrupt Mask Clear Register */
    volatile Uint32 NIMCR;
    /** NAND Flash Control Register */
    volatile Uint32 NANDFCR;
    /** IODFT Test Logic Execution Counter Register */
    volatile Uint32 IODFTECR;
    /** IODFT Test Logic Global Control Register */
    volatile Uint32 IODFTGCR;
    /** NAND DATA Address for NAND_/CE0 */
    volatile Uint32 CE0DATA;
    /** NAND ALE Address for NAND_/CE0 */
    volatile Uint32 CE0ALE;
    /** NAND CLE Address for NAND_/CE0 */
    volatile Uint32 CE0CLE;
    /** NAND DATA Address for NAND_/CE1 */
    volatile Uint32 CE1DATA;
    /** NAND ALE Address for NAND_/CE1 */
    volatile Uint32 CE1ALE;
    /** NAND CLE Address for NAND_/CE1 */
    volatile Uint32 CE1CLE;
    /** NAND DATA Address for NAND_/CE2 */
    volatile Uint32 CE2DATA;
    /** NAND ALE Address for NAND_/CE2 */
    volatile Uint32 CE2ALE;
    /** NAND CLE Address for NAND_/CE2 */
    volatile Uint32 CE2CLE;
    /** NAND DATA Address for NAND_/CE3 */
    volatile Uint32 CE3DATA;
    /** NAND ALE Address for NAND_/CE3 */
    volatile Uint32 CE3ALE;
    /** NAND CLE Address for NAND_/CE3 */
    volatile Uint32 CE3CLE;
} CSL_NandConfig;

/** Default Values for Config structure */
#define CSL_NAND_CONFIG_DEFAULTS {  \
    CSL_NAND_AWCCR_RESETVAL,     \
    CSL_NAND_AB1CR_RESETVAL,     \
    CSL_NAND_AB2CR_RESETVAL,     \
    CSL_NAND_AB3CR_RESETVAL,     \
    CSL_NAND_AB4CR_RESETVAL,     \
    CSL_NAND_NIRR_RESETVAL ,     \
    CSL_NAND_NIMR_RESETVAL ,     \
    CSL_NAND_NIMSR_RESETVAL,     \
    CSL_NAND_NIMCR_RESETVAL,     \
    CSL_NAND_NANDFCR_RESETVAL,   \
    CSL_NAND_IODFTECR_RESETVAL,  \
    CSL_NAND_IODFTGCR_RESETVAL,  \
    CSL_NAND_CE0DATA_RESETVAL,   \
    CSL_NAND_CE0ALE_RESETVAL,    \
    CSL_NAND_CE0CLE_RESETVAL,    \
    CSL_NAND_CE1DATA_RESETVAL,   \
    CSL_NAND_CE1ALE_RESETVAL,    \
    CSL_NAND_CE1CLE_RESETVAL,    \
    CSL_NAND_CE2DATA_RESETVAL,   \
    CSL_NAND_CE2ALE_RESETVAL,    \
    CSL_NAND_CE2CLE_RESETVAL,    \
    CSL_NAND_CE3DATA_RESETVAL,   \
    CSL_NAND_CE3ALE_RESETVAL,    \
    CSL_NAND_CE3CLE_RESETVAL     \
}

/** @brief This data type is used to return the handle to the CSL of NAND
 */
typedef struct CSL_NandObj *CSL_NandHandle;

/** @brief Asynchronous Wait Cycle Configuration structure
*
* All fields needed for Async Wait Cycle configuration are present in this
* structure.
*/
typedef struct {
    /** Wait polarity for pad_wait_i[3]*/
    Uint16 wp3;
    /** Wait polarity for pad_wait_i[2]*/
    Uint16 wp2;
    /** Wait polarity for pad_wait_i[1]*/
    Uint16 wp1;
    /** Wait polarity for pad_wait_i[0]*/
    Uint16 wp0;
    /** pad_wait_i map bits for chip select 5 */
    Uint16 cs3Wait;
    /** pad_wait_i map bits for chip select 4 */
    Uint16 cs2Wait;
     /** pad_wait_i map bits for chip select 3 */
    Uint16 cs1Wait;
     /** pad_wait_i map bits for chip select 2 */
    Uint16 cs0Wait;
    /** Maximum external wait cycles */
    Uint16 maxExtWait;
}CSL_NandAsyncWaitCycleConfig;

/** @brief Asynchronous Bank Configuration structure
*
* All fields needed for Async Bank configuration are present in this structure.
*/
typedef struct {
    /** Select strobe mode */
    Uint16 selectStrobe;
    /** Extend wait mode */
    Uint16 extWait;
    /** Write strobe setup cycles */
    Uint16 writeSetup;
    /** Write strobe duration cycles */
    Uint16 writeStrobe;
    /** Write strobe hold cycles */
    Uint16 writeHold;
    /** Read strobe setup cycles */
    Uint16 readSetup;
     /** Read strobe duration cycles */
    Uint16 readStrobe;
     /** Read strobe hold cycles */
    Uint16 readHold;
     /** Turnaround cycles */
    Uint16 turnAround;
    /** Asyncronous Bank size */
    Uint16 asyncSize;
}CSL_NandAsyncBankConfig;

/** @brief  NAND FLASH Control Register structure
*
*  All fields needed for NAND FLASH Control are present in this structure.
*/
typedef struct {
    /** Chip select 5 Nand */
    Uint16 cs5nand;
    /** Chip select 4 Nand */
    Uint16 cs4nand;
    /** Chip select 3 Nand */
    Uint16 cs3nand;
    /** Chip select 2 Nand */
    Uint16 cs2nand;
}CSL_NandFlashControl;

/** @brief This has all the fields required to configure NAND at Power Up
 *  (After a Hardware Reset) or a Soft Reset
 *
 *  This structure is used to setup or obtain existing setup of
 *  NAND using @a CSL_nandHwSetup() & @a CSL_nandGetHwSetup() functions
 *  respectively.
 */
typedef struct {
    /** Structure for Async Wait Cycle configuration */
    CSL_NandAsyncWaitCycleConfig  *asyncWaitCycleConfig;
    /** Structure for Async Bank 1 Config Registers */
    CSL_NandAsyncBankConfig *asyncBank1Config;
    /** Structure for Async Bank 2 Config Registers */
    CSL_NandAsyncBankConfig *asyncBank2Config;
    /** Structure for Async Bank 3 Config Registers */
    CSL_NandAsyncBankConfig *asyncBank3Config;
    /** Structure for Async Bank 4 Config Registers */
    CSL_NandAsyncBankConfig *asyncBank4Config;
    /** Structure for NAND FLASH control */
    CSL_NandFlashControl *nandFlashControl;
    /** Base address for NAND device */
    Uint32                nandBaseAddress;
}CSL_NandHwSetup;

/** @brief NAND Module ID and Revision structure
*
*  This structure is used for querying the NAND module ID and revision
*/
typedef struct {
    /** NAND Module ID */
    Uint16 moduleID;
    /** NAND Major Revision */
    Uint16 majorRev;
    /** NAND Minor Revision */
    Uint16 minorRev;
}CSL_NandRevStatus;

/** @brief NAND FLASH ECC structure
*
* This structure holds the fields in the Nand Flash ECC Register.
*/
typedef struct {
    /** ECC code calculated while reading/writing NAND Flash.
      For 8_bit NAND Flash, p1o, p2o, and p4o are column parities. p8o to
      p2048o are row parities.For 16_bit NAND Flash, p1o, p2o, p4o and p8o 
      are column parities. p16o to p2048o are row parities.
      Odd Polarity for p2048 */ 
    Uint16 p2048o; 
    
    /** Odd Polarity for p1024 */
    Uint16 p1024o;
    
    /** Odd Polarity for p512 */
    Uint16 p512o;
    
    /** Odd Polarity for p256 */
    Uint16 p256o;
    
    /** Odd Polarity for p128 */
    Uint16 p128o;
    
    /** Odd Polarity for p64 */
    Uint16 p64o;
    
    /** Odd Polarity for p32 */
    Uint16 p32o;
    
    /** Odd Polarity for p16 */