cslr_wdt.h

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */

 /** \file cslr_wdt.h
 * 
 * \brief This file contains the Register Desciptions for WDT
 *  Path: \\(CSLPATH)\\soc\\davinci\\arm9\\src 
 *********************************************************************/

#ifndef _CSLR_WDT_H_
#define _CSLR_WDT_H_


#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 PID12;
    volatile Uint32 EMUMGT_CLKSPD;
    volatile Uint32 GPINT_GPEN;
    volatile Uint32 GPTDAT_GPDIR;
    volatile Uint32 TIM12;
    volatile Uint32 TIM34;
    volatile Uint32 PRD12;
    volatile Uint32 PRD34;
    volatile Uint32 TCR;
    volatile Uint32 TGCR;
    volatile Uint32 WDTCR;
} CSL_WdtRegs;

/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_WdtRegs *CSL_WdtRegsOvly;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* PID12 */

#define CSL_WDT_PID12_TYPE_MASK          (0x007F0000u)
#define CSL_WDT_PID12_TYPE_SHIFT         (0x00000010u)
#define CSL_WDT_PID12_TYPE_RESETVAL      (0x00000001u)

#define CSL_WDT_PID12_CLASS_MASK         (0x0000FF00u)
#define CSL_WDT_PID12_CLASS_SHIFT        (0x00000008u)
#define CSL_WDT_PID12_CLASS_RESETVAL     (0x00000007u)

#define CSL_WDT_PID12_REVISION_MASK      (0x000000FFu)
#define CSL_WDT_PID12_REVISION_SHIFT     (0x00000000u)
#define CSL_WDT_PID12_REVISION_RESETVAL  (0x00000001u)

#define CSL_WDT_PID12_RESETVAL           (0x00010701u)

/* EMUMGT_CLKSPD */

#define CSL_WDT_EMUMGT_CLKSPD_CLKDIV_MASK (0x000F0000u)
#define CSL_WDT_EMUMGT_CLKSPD_CLKDIV_SHIFT (0x00000010u)
#define CSL_WDT_EMUMGT_CLKSPD_CLKDIV_RESETVAL (0x00000000u)

#define CSL_WDT_EMUMGT_CLKSPD_SOFT_MASK  (0x00000002u)
#define CSL_WDT_EMUMGT_CLKSPD_SOFT_SHIFT (0x00000001u)
#define CSL_WDT_EMUMGT_CLKSPD_SOFT_RESETVAL (0x00000000u)

/*----SOFT Tokens----*/
#define CSL_WDT_EMUMGT_CLKSPD_SOFT_OFF   (0x00000000u)
#define CSL_WDT_EMUMGT_CLKSPD_SOFT_ON    (0x00000001u)
            
#define CSL_WDT_EMUMGT_CLKSPD_FREE_MASK  (0x00000001u)
#define CSL_WDT_EMUMGT_CLKSPD_FREE_SHIFT (0x00000000u)
#define CSL_WDT_EMUMGT_CLKSPD_FREE_RESETVAL (0x00000000u)

/*----FREE Tokens----*/
#define CSL_WDT_EMUMGT_CLKSPD_FREE_ON    (0x00000000u)
#define CSL_WDT_EMUMGT_CLKSPD_FREE_OFF   (0x00000001u)
            
#define CSL_WDT_EMUMGT_CLKSPD_RESETVAL   (0x00000000u)

/* GPINT_GPEN */

#define CSL_WDT_GPINT_GPEN_GPIO_ENO34_MASK (0x02000000u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENO34_SHIFT (0x00000019u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENO34_RESETVAL (0x00000000u)

/*----GPIO_ENO34 Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPIO_ENO34_TIMER_OUTPUT (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENO34_GPIO_PIN (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPIO_ENI34_MASK (0x01000000u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENI34_SHIFT (0x00000018u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENI34_RESETVAL (0x00000000u)

/*----GPIO_ENI34 Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPIO_ENI34_TIMER_INPUT (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENI34_GPIO_PIN (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPIO_ENO12_MASK (0x00020000u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENO12_SHIFT (0x00000011u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENO12_RESETVAL (0x00000000u)

/*----GPIO_ENO12 Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPIO_ENO12_TIMER_OUTPUT (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENO12_GPIO_PIN (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPIO_ENI12_MASK (0x00010000u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENI12_SHIFT (0x00000010u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENI12_RESETVAL (0x00000000u)

/*----GPIO_ENI12 Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPIO_ENI12_TIMER_INPUT (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPIO_ENI12_GPIO_PIN (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPINT34_INVO_MASK (0x00002000u)
#define CSL_WDT_GPINT_GPEN_GPINT34_INVO_SHIFT (0x0000000Du)
#define CSL_WDT_GPINT_GPEN_GPINT34_INVO_RESETVAL (0x00000000u)

/*----GPINT34_INVO Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPINT34_INVO_DISABLE (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPINT34_INVO_ENABLE (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPINT34_INVI_MASK (0x00001000u)
#define CSL_WDT_GPINT_GPEN_GPINT34_INVI_SHIFT (0x0000000Cu)
#define CSL_WDT_GPINT_GPEN_GPINT34_INVI_RESETVAL (0x00000000u)

/*----GPINT34_INVI Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPINT34_INVI_DISABLE (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPINT34_INVI_ENABLE (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPINT34_ENO_MASK (0x00000200u)
#define CSL_WDT_GPINT_GPEN_GPINT34_ENO_SHIFT (0x00000009u)
#define CSL_WDT_GPINT_GPEN_GPINT34_ENO_RESETVAL (0x00000000u)

/*----GPINT34_ENO Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPINT34_ENO_DISABLE (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPINT34_ENO_ENABLE (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPINT34_ENI_MASK (0x00000100u)
#define CSL_WDT_GPINT_GPEN_GPINT34_ENI_SHIFT (0x00000008u)
#define CSL_WDT_GPINT_GPEN_GPINT34_ENI_RESETVAL (0x00000000u)

/*----GPINT34_ENI Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPINT34_ENI_DISABLE (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPINT34_ENI_ENABLE (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPINT12_INVO_MASK (0x00000020u)
#define CSL_WDT_GPINT_GPEN_GPINT12_INVO_SHIFT (0x00000005u)
#define CSL_WDT_GPINT_GPEN_GPINT12_INVO_RESETVAL (0x00000000u)

/*----GPINT12_INVO Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPINT12_INVO_DISABLE (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPINT12_INVO_ENABLE (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPINT12_INVI_MASK (0x00000010u)
#define CSL_WDT_GPINT_GPEN_GPINT12_INVI_SHIFT (0x00000004u)
#define CSL_WDT_GPINT_GPEN_GPINT12_INVI_RESETVAL (0x00000000u)

/*----GPINT12_INVI Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPINT12_INVI_DISABLE (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPINT12_INVI_ENABLE (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPINT12_ENO_MASK (0x00000002u)
#define CSL_WDT_GPINT_GPEN_GPINT12_ENO_SHIFT (0x00000001u)
#define CSL_WDT_GPINT_GPEN_GPINT12_ENO_RESETVAL (0x00000000u)

/*----GPINT12_ENO Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPINT12_ENO_DISABLE (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPINT12_ENO_ENABLE (0x00000001u)

#define CSL_WDT_GPINT_GPEN_GPINT12_ENI_MASK (0x00000001u)
#define CSL_WDT_GPINT_GPEN_GPINT12_ENI_SHIFT (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPINT12_ENI_RESETVAL (0x00000000u)

/*----GPINT12_ENI Tokens----*/
#define CSL_WDT_GPINT_GPEN_GPINT12_ENI_DISABLE (0x00000000u)
#define CSL_WDT_GPINT_GPEN_GPINT12_ENI_ENABLE (0x00000001u)

#define CSL_WDT_GPINT_GPEN_RESETVAL      (0x00000000u)

/* GPTDAT_GPDIR */

#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO34_MASK (0x02000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO34_SHIFT (0x00000019u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO34_RESETVAL (0x00000000u)

/*----GPIO_DIRO34 Tokens----*/
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO34_TIMER_OUTPUT (0x00000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO34_GPIO_PIN (0x00000001u)

#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI34_MASK (0x01000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI34_SHIFT (0x00000018u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI34_RESETVAL (0x00000000u)

/*----GPIO_DIRI34 Tokens----*/
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI34_TIMER_INPUT (0x00000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI34_GPIO_PIN (0x00000001u)

#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO12_MASK (0x00020000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO12_SHIFT (0x00000011u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO12_RESETVAL (0x00000000u)

/*----GPIO_DIRO12 Tokens----*/
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO12_TIMER_OUTPUT (0x00000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRO12_GPIO_PIN (0x00000001u)

#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI12_MASK (0x00010000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI12_SHIFT (0x00000010u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI12_RESETVAL (0x00000000u)

/*----GPIO_DIRI12 Tokens----*/
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI12_TIMER_INPUT (0x00000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DIRI12_GPIO_PIN (0x00000001u)

#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO34_MASK (0x00000200u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO34_SHIFT (0x00000009u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO34_RESETVAL (0x00000000u)

/*----GPIO_DATO34 Tokens----*/
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO34_DISABLE (0x00000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO34_ENABLE (0x00000001u)

#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATI34_MASK (0x00000100u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATI34_SHIFT (0x00000008u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATI34_RESETVAL (0x00000000u)

/*----GPIO_DATI34 Tokens----*/
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATI34_DISABLE (0x00000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATI34_ENABLE (0x00000001u)

#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO12_MASK (0x00000002u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO12_SHIFT (0x00000001u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO12_RESETVAL (0x00000000u)

/*----GPIO_DATO12 Tokens----*/
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO12_DISABLE (0x00000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATO12_ENABLE (0x00000001u)

#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATI12_MASK (0x00000001u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATI12_SHIFT (0x00000000u)
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATI12_RESETVAL (0x00000000u)

/*----GPIO_DATI12 Tokens----*/
#define CSL_WDT_GPTDAT_GPDIR_GPIO_DATI12_DISABLE (0x00000000u)