soc.h

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */

/* =============================================================================
 *  Revision History
 *  ================
 *  24-Feb-2005 BRN Defined CSL_IDEF_INLINE for static inline and made changes 
 *                  in interrupt controller event ids definitions when merging 
 *                  the changes from DaVinci Release 0.52 to 0.57
 *  09-Feb-2005 KPN Added code for PMX module
 *  04-Feb-2005 BRN Updated according to VPDAVINCI base addresses
 *  28-Jan-2005 KPN Updated according to new soc.h structure
 *  22-Dec-2004 Nsr created this file from hibari.h
 * =============================================================================
 */

#ifndef _SOC_H
#define _SOC_H

/*****************************************************************************/
/** \file soc.h
 *
 * \brief This file contains the Chip Description for DAVINCI (ARM side)
 *
 *****************************************************************************/

#include <cslr.h>


#define CSL_IDEF_INLINE static inline
/*****************************************************************************\
* Peripheral Instance counts
\*****************************************************************************/

#define CSL_UART_CNT                 3
#define CSL_I2C_CNT                  1
#define CSL_TMR_CNT                  4
#define CSL_WDT_CNT                  1
#define CSL_PWM_CNT                  3
#define CSL_PLLC_CNT                 2
#define CSL_PWR_SLEEP_CTRL_CNT       1
#define CSL_SYS_DFT_CNT              1
#define CSL_INTC_CNT                 1
#define CSL_IEEE1394_CNT             1
#define CSL_USBOTG_CNT               1
#define CSL_ATA_CNT                  1
#define CSL_SPI_CNT                  1
#define CSL_GPIO_CNT                 1
#define CSL_UHPI_CNT                 1
#define CSL_VPSS_REGS_CNT            1
#define CSL_EMAC_CTRL_CNT            1
#define CSL_EMAC_WRAP_CNT            1
#define CSL_EMAC_RAM_CNT             1
#define CSL_MDIO_CNT                 1
#define CSL_EMIF_CNT                 1
#define CSL_NAND_CNT                 1
#define CSL_MCBSP_CNT                1
#define CSL_MMCSD_CNT                1
#define CSL_MS_CNT                   1
#define CSL_DDR_CNT                  1
#define CSL_VLYNQ_CNT                1
#define CSL_PMX_CNT                  1

/*****************************************************************************\
* Peripheral Instance enumeration
\*****************************************************************************/

/** @brief Peripheral Instance for UART  */
#define CSL_UART_1                          (0) /** Instance 1 of UART   */

/** @brief Peripheral Instance for UART  */
#define CSL_UART_2                          (1) /** Instance 2 of UART   */

/** @brief Peripheral Instance for UART  */
#define CSL_UART_3                          (2) /** Instance 3 of UART   */

/** @brief Peripheral Instance for I2C   */
#define CSL_I2C                             (0) /** Instance 1 of I2C    */

/** @brief Peripheral Instance for Tmr0  */
#define CSL_TMR_1                           (0) /** Instance 1 of Tmr    */

/** @brief Peripheral Instance for Tmr1  */
#define CSL_TMR_2                           (1) /** Instance 2 of Tmr    */

/** @brief Peripheral Instance for Tmr2  */
#define CSL_TMR_3                           (2) /** Instance 3 of Tmr    */

/** @brief Peripheral Instance for Tmr3  */
#define CSL_TMR_4                           (3) /** Instance 4 of Tmr    */

/** @brief Peripheral Instance for WDT   */
#define CSL_WDT                             (0) /** Instance of WDT      */

/** @brief Peripheral Instance for PWM   */
#define CSL_PWM_1                           (0) /** Instance 1 of PWM    */

/** @brief Peripheral Instance for PWM   */
#define CSL_PWM_2                           (1) /** Instance 2 of PWM    */

/** @brief Peripheral Instance for PWM   */
#define CSL_PWM_3                           (2) /** Instance 3 of PWM    */

/** @brief Peripheral Instance for PLLC  */
#define CSL_PLLC_1                          (0) /** Instance 1 of PLLC   */

/** @brief Peripheral Instance for PLLC  */
#define CSL_PLLC_2                          (1) /** Instance 2 of PLLC   */

/** @brief Peripheral Instance for CSL_PWR_SLEEP_CTRL  */
#define CSL_PWR_SLEEP_CTRL                  (0) /** Instance 1 of PWR_SLEEP_CTRL    */
#define CSL_PSC                             (0)

/** @brief Peripheral Instance for SYS_DFT  */
#define CSL_SYS_DFT                         (0) /** Instance 1 of SYS_DFT*/

/** @brief Peripheral Instance for INTC   */
#define CSL_INTC                            (0) /** Instance 1 of INTC   */

/** @brief Peripheral Instance for IEEE 1394  */
#define CSL_IEEE1394                       (0) /** Instance 1 of IEEE 1394     */

/** @brief Peripheral Instance for USBOTG  */
#define CSL_USBOTG                          (0) /** Instance 1 of USBOTG */

/** @brief Peripheral Instance for ATA   */
#define CSL_ATA_PRIMARY                     (0) /** Instance 1 of ATA    */

/** @brief Peripheral Instance for ATA   */
#define CSL_ATA_SECONDARY                   (1) /** Instance 2 of ATA    */

/** @brief Peripheral Instance for SPI   */
#define CSL_SPI                             (0) /** Instance 1 of SPI    */

/** @brief Peripheral Instance for GPIO  */
#define CSL_GPIO                            (0) /** Instance 1 of GPIO   */

/** @brief Peripheral Instance for UHPI  */
#define CSL_UHPI                            (0) /** Instance 1 of UHPI   */

/** @brief Peripheral Instance for VPSS_REGS  */
#define CSL_VPSS_REGS                       (0) /** Instance 1 of VPSS_REGS     */

/** @brief Peripheral Instance for EMAC_CTRL  */
#define CSL_EMAC_CTRL                       (0) /** Instance 1 of EMAC_CTRL     */

/** @brief Peripheral Instance for EMAC_WRAP  */
#define CSL_EMAC_WRAP                       (0) /** Instance 1 of EMAC_WRAP     */

/** @brief Peripheral Instance for EMAC_RAM  */
#define CSL_EMAC_RAM                        (0) /** Instance 1 of EMAC_RAM      */

/** @brief Peripheral Instance for MDIO  */
#define CSL_MDIO                            (0) /** Instance 1 of MDIO   */

/** @brief Peripheral Instance for EMIF  */
#define CSL_EMIF                            (0) /** Instance 1 of EMIF   */

/** @brief Peripheral Instance for NAND  */
#define CSL_NAND                            (0) /** Instance 1 of NAND   */

/** @brief Peripheral Instance for MCBSP */
#define CSL_MCBSP                           (0) /** Instance 1 of MCBSP  */