cslr_nand.h

TI达芬奇dm644x各硬件模块测试代码

#define CSL_NAND_NANDF3ECC_P8O_MASK      (0x00080000u)
#define CSL_NAND_NANDF3ECC_P8O_SHIFT     (0x00000013u)
#define CSL_NAND_NANDF3ECC_P8O_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF3ECC_P4O_MASK      (0x00040000u)
#define CSL_NAND_NANDF3ECC_P4O_SHIFT     (0x00000012u)
#define CSL_NAND_NANDF3ECC_P4O_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF3ECC_P2O_MASK      (0x00020000u)
#define CSL_NAND_NANDF3ECC_P2O_SHIFT     (0x00000011u)
#define CSL_NAND_NANDF3ECC_P2O_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF3ECC_P1O_MASK      (0x00010000u)
#define CSL_NAND_NANDF3ECC_P1O_SHIFT     (0x00000010u)
#define CSL_NAND_NANDF3ECC_P1O_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF3ECC_P2048E_MASK   (0x00000800u)
#define CSL_NAND_NANDF3ECC_P2048E_SHIFT  (0x0000000Bu)
#define CSL_NAND_NANDF3ECC_P2048E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF3ECC_P1024E_MASK   (0x00000400u)
#define CSL_NAND_NANDF3ECC_P1024E_SHIFT  (0x0000000Au)
#define CSL_NAND_NANDF3ECC_P1024E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF3ECC_P512E_MASK    (0x00000200u)
#define CSL_NAND_NANDF3ECC_P512E_SHIFT   (0x00000009u)
#define CSL_NAND_NANDF3ECC_P512E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF3ECC_P256E_MASK    (0x00000100u)
#define CSL_NAND_NANDF3ECC_P256E_SHIFT   (0x00000008u)
#define CSL_NAND_NANDF3ECC_P256E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF3ECC_P128E_MASK    (0x00000080u)
#define CSL_NAND_NANDF3ECC_P128E_SHIFT   (0x00000007u)
#define CSL_NAND_NANDF3ECC_P128E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF3ECC_P64E_MASK     (0x00000040u)
#define CSL_NAND_NANDF3ECC_P64E_SHIFT    (0x00000006u)
#define CSL_NAND_NANDF3ECC_P64E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF3ECC_P32E_MASK     (0x00000020u)
#define CSL_NAND_NANDF3ECC_P32E_SHIFT    (0x00000005u)
#define CSL_NAND_NANDF3ECC_P32E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF3ECC_P16E_MASK     (0x00000010u)
#define CSL_NAND_NANDF3ECC_P16E_SHIFT    (0x00000004u)
#define CSL_NAND_NANDF3ECC_P16E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF3ECC_P8E_MASK      (0x00000008u)
#define CSL_NAND_NANDF3ECC_P8E_SHIFT     (0x00000003u)
#define CSL_NAND_NANDF3ECC_P8E_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF3ECC_P4E_MASK      (0x00000004u)
#define CSL_NAND_NANDF3ECC_P4E_SHIFT     (0x00000002u)
#define CSL_NAND_NANDF3ECC_P4E_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF3ECC_P2E_MASK      (0x00000002u)
#define CSL_NAND_NANDF3ECC_P2E_SHIFT     (0x00000001u)
#define CSL_NAND_NANDF3ECC_P2E_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF3ECC_P1E_MASK      (0x00000001u)
#define CSL_NAND_NANDF3ECC_P1E_SHIFT     (0x00000000u)
#define CSL_NAND_NANDF3ECC_P1E_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF3ECC_RESETVAL      (0x00000000u)

/* NANDF4ECC */

#define CSL_NAND_NANDF4ECC_P2048O_MASK   (0x08000000u)
#define CSL_NAND_NANDF4ECC_P2048O_SHIFT  (0x0000001Bu)
#define CSL_NAND_NANDF4ECC_P2048O_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P1024O_MASK   (0x04000000u)
#define CSL_NAND_NANDF4ECC_P1024O_SHIFT  (0x0000001Au)
#define CSL_NAND_NANDF4ECC_P1024O_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P512O_MASK    (0x02000000u)
#define CSL_NAND_NANDF4ECC_P512O_SHIFT   (0x00000019u)
#define CSL_NAND_NANDF4ECC_P512O_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P256O_MASK    (0x01000000u)
#define CSL_NAND_NANDF4ECC_P256O_SHIFT   (0x00000018u)
#define CSL_NAND_NANDF4ECC_P256O_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P128O_MASK    (0x00800000u)
#define CSL_NAND_NANDF4ECC_P128O_SHIFT   (0x00000017u)
#define CSL_NAND_NANDF4ECC_P128O_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P64O_MASK     (0x00400000u)
#define CSL_NAND_NANDF4ECC_P64O_SHIFT    (0x00000016u)
#define CSL_NAND_NANDF4ECC_P64O_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P32O_MASK     (0x00200000u)
#define CSL_NAND_NANDF4ECC_P32O_SHIFT    (0x00000015u)
#define CSL_NAND_NANDF4ECC_P32O_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P16O_MASK     (0x00100000u)
#define CSL_NAND_NANDF4ECC_P16O_SHIFT    (0x00000014u)
#define CSL_NAND_NANDF4ECC_P16O_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P8O_MASK      (0x00080000u)
#define CSL_NAND_NANDF4ECC_P8O_SHIFT     (0x00000013u)
#define CSL_NAND_NANDF4ECC_P8O_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF4ECC_P4O_MASK      (0x00040000u)
#define CSL_NAND_NANDF4ECC_P4O_SHIFT     (0x00000012u)
#define CSL_NAND_NANDF4ECC_P4O_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF4ECC_P2O_MASK      (0x00020000u)
#define CSL_NAND_NANDF4ECC_P2O_SHIFT     (0x00000011u)
#define CSL_NAND_NANDF4ECC_P2O_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF4ECC_P1O_MASK      (0x00010000u)
#define CSL_NAND_NANDF4ECC_P1O_SHIFT     (0x00000010u)
#define CSL_NAND_NANDF4ECC_P1O_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF4ECC_P2048E_MASK   (0x00000800u)
#define CSL_NAND_NANDF4ECC_P2048E_SHIFT  (0x0000000Bu)
#define CSL_NAND_NANDF4ECC_P2048E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P1024E_MASK   (0x00000400u)
#define CSL_NAND_NANDF4ECC_P1024E_SHIFT  (0x0000000Au)
#define CSL_NAND_NANDF4ECC_P1024E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P512E_MASK    (0x00000200u)
#define CSL_NAND_NANDF4ECC_P512E_SHIFT   (0x00000009u)
#define CSL_NAND_NANDF4ECC_P512E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P256E_MASK    (0x00000100u)
#define CSL_NAND_NANDF4ECC_P256E_SHIFT   (0x00000008u)
#define CSL_NAND_NANDF4ECC_P256E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P128E_MASK    (0x00000080u)
#define CSL_NAND_NANDF4ECC_P128E_SHIFT   (0x00000007u)
#define CSL_NAND_NANDF4ECC_P128E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P64E_MASK     (0x00000040u)
#define CSL_NAND_NANDF4ECC_P64E_SHIFT    (0x00000006u)
#define CSL_NAND_NANDF4ECC_P64E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P32E_MASK     (0x00000020u)
#define CSL_NAND_NANDF4ECC_P32E_SHIFT    (0x00000005u)
#define CSL_NAND_NANDF4ECC_P32E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P16E_MASK     (0x00000010u)
#define CSL_NAND_NANDF4ECC_P16E_SHIFT    (0x00000004u)
#define CSL_NAND_NANDF4ECC_P16E_RESETVAL (0x00000000u)

#define CSL_NAND_NANDF4ECC_P8E_MASK      (0x00000008u)
#define CSL_NAND_NANDF4ECC_P8E_SHIFT     (0x00000003u)
#define CSL_NAND_NANDF4ECC_P8E_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF4ECC_P4E_MASK      (0x00000004u)
#define CSL_NAND_NANDF4ECC_P4E_SHIFT     (0x00000002u)
#define CSL_NAND_NANDF4ECC_P4E_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF4ECC_P2E_MASK      (0x00000002u)
#define CSL_NAND_NANDF4ECC_P2E_SHIFT     (0x00000001u)
#define CSL_NAND_NANDF4ECC_P2E_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF4ECC_P1E_MASK      (0x00000001u)
#define CSL_NAND_NANDF4ECC_P1E_SHIFT     (0x00000000u)
#define CSL_NAND_NANDF4ECC_P1E_RESETVAL  (0x00000000u)

#define CSL_NAND_NANDF4ECC_RESETVAL      (0x00000000u)

/* IODFTECR */

#define CSL_NAND_IODFTECR_TLEC_MASK      (0x0000FFFFu)
#define CSL_NAND_IODFTECR_TLEC_SHIFT     (0x00000000u)
#define CSL_NAND_IODFTECR_TLEC_RESETVAL  (0x00000000u)

#define CSL_NAND_IODFTECR_RESETVAL       (0x00000000u)

/* IODFTGCR */

#define CSL_NAND_IODFTGCR_MT_MASK        (0x00004000u)
#define CSL_NAND_IODFTGCR_MT_SHIFT       (0x0000000Eu)
#define CSL_NAND_IODFTGCR_MT_RESETVAL    (0x00000000u)

#define CSL_NAND_IODFTGCR_OPGLD_MASK     (0x00001000u)
#define CSL_NAND_IODFTGCR_OPGLD_SHIFT    (0x0000000Cu)
#define CSL_NAND_IODFTGCR_OPGLD_RESETVAL (0x00000000u)

#define CSL_NAND_IODFTGCR_MMS_MASK       (0x00000100u)
#define CSL_NAND_IODFTGCR_MMS_SHIFT      (0x00000008u)
#define CSL_NAND_IODFTGCR_MMS_RESETVAL   (0x00000000u)

#define CSL_NAND_IODFTGCR_ESEL_MASK      (0x00000080u)
#define CSL_NAND_IODFTGCR_ESEL_SHIFT     (0x00000007u)
#define CSL_NAND_IODFTGCR_ESEL_RESETVAL  (0x00000001u)

#define CSL_NAND_IODFTGCR_TOEN_MASK      (0x00000040u)
#define CSL_NAND_IODFTGCR_TOEN_SHIFT     (0x00000006u)
#define CSL_NAND_IODFTGCR_TOEN_RESETVAL  (0x00000000u)

#define CSL_NAND_IODFTGCR_MC_MASK        (0x00000030u)
#define CSL_NAND_IODFTGCR_MC_SHIFT       (0x00000004u)
#define CSL_NAND_IODFTGCR_MC_RESETVAL    (0x00000001u)

#define CSL_NAND_IODFTGCR_PC_MASK        (0x0000000Eu)
#define CSL_NAND_IODFTGCR_PC_SHIFT       (0x00000001u)
#define CSL_NAND_IODFTGCR_PC_RESETVAL    (0x00000000u)

#define CSL_NAND_IODFTGCR_TM_MASK        (0x00000001u)
#define CSL_NAND_IODFTGCR_TM_SHIFT       (0x00000000u)
#define CSL_NAND_IODFTGCR_TM_RESETVAL    (0x00000001u)

#define CSL_NAND_IODFTGCR_RESETVAL       (0x00000091u)

/* IODFTMRLR */

#define CSL_NAND_IODFTMRLR_TLMR_MASK     (0xFFFFFFFFu)
#define CSL_NAND_IODFTMRLR_TLMR_SHIFT    (0x00000000u)
#define CSL_NAND_IODFTMRLR_TLMR_RESETVAL (0x00000000u)

#define CSL_NAND_IODFTMRLR_RESETVAL      (0x00000000u)

/* IODFTMRMR */

#define CSL_NAND_IODFTMRMR_TLMR_MASK     (0xFFFFFFFFu)
#define CSL_NAND_IODFTMRMR_TLMR_SHIFT    (0x00000000u)
#define CSL_NAND_IODFTMRMR_TLMR_RESETVAL (0x00000000u)

#define CSL_NAND_IODFTMRMR_RESETVAL      (0x00000000u)

/* IODFTMRMSBR */

#define CSL_NAND_IODFTMRMSBR_TLMR_MASK   (0xFFFFFFFFu)
#define CSL_NAND_IODFTMRMSBR_TLMR_SHIFT  (0x00000000u)
#define CSL_NAND_IODFTMRMSBR_TLMR_RESETVAL (0x00000000u)

#define CSL_NAND_IODFTMRMSBR_RESETVAL    (0x00000000u)

/* MODRNR */

#define CSL_NAND_MODRNR_RLNUM_MASK       (0x000000FFu)
#define CSL_NAND_MODRNR_RLNUM_SHIFT      (0x00000000u)
#define CSL_NAND_MODRNR_RLNUM_RESETVAL   (0x00000003u)

//#define CSL_NAND_MODRNR_RESETVAL         (0x00000003u)
#define CSL_NAND_MODRNR_RESETVAL         (0x00000005u)

/* CE0DATA */

#define CSL_NAND_CE0DATA_ADDR_MASK       (0xFFFFFFFFu)
#define CSL_NAND_CE0DATA_ADDR_SHIFT      (0x00000000u)
#define CSL_NAND_CE0DATA_ADDR_RESETVAL   (0x00000000u)

#define CSL_NAND_CE0DATA_RESETVAL        (0x00000000u)

/* CE0ALE */

#define CSL_NAND_CE0ALE_ADDR_MASK        (0xFFFFFFFFu)
#define CSL_NAND_CE0ALE_ADDR_SHIFT       (0x00000000u)
#define CSL_NAND_CE0ALE_ADDR_RESETVAL    (0x00000000u)

#define CSL_NAND_CE0ALE_RESETVAL         (0x00000000u)

/* CE0CLE */

#define CSL_NAND_CE0CLE_ADDR_MASK        (0xFFFFFFFFu)
#define CSL_NAND_CE0CLE_ADDR_SHIFT       (0x00000000u)
#define CSL_NAND_CE0CLE_ADDR_RESETVAL    (0x00000000u)

#define CSL_NAND_CE0CLE_RESETVAL         (0x00000000u)

/* CE1DATA */

#define CSL_NAND_CE1DATA_ADDR_MASK       (0xFFFFFFFFu)
#define CSL_NAND_CE1DATA_ADDR_SHIFT      (0x00000000u)
#define CSL_NAND_CE1DATA_ADDR_RESETVAL   (0x00000000u)

#define CSL_NAND_CE1DATA_RESETVAL        (0x00000000u)

/* CE1ALE */

#define CSL_NAND_CE1ALE_ADDR_MASK        (0xFFFFFFFFu)
#define CSL_NAND_CE1ALE_ADDR_SHIFT       (0x00000000u)
#define CSL_NAND_CE1ALE_ADDR_RESETVAL    (0x00000000u)

#define CSL_NAND_CE1ALE_RESETVAL         (0x00000000u)

/* CE1CLE */

#define CSL_NAND_CE1CLE_ADDR_MASK        (0xFFFFFFFFu)
#define CSL_NAND_CE1CLE_ADDR_SHIFT       (0x00000000u)
#define CSL_NAND_CE1CLE_ADDR_RESETVAL    (0x00000000u)

#define CSL_NAND_CE1CLE_RESETVAL         (0x00000000u)

/* CE2DATA */

#define CSL_NAND_CE2DATA_ADDR_MASK       (0xFFFFFFFFu)
#define CSL_NAND_CE2DATA_ADDR_SHIFT      (0x00000000u)
#define CSL_NAND_CE2DATA_ADDR_RESETVAL   (0x00000000u)

#define CSL_NAND_CE2DATA_RESETVAL        (0x00000000u)

/* CE2ALE */

#define CSL_NAND_CE2ALE_ADDR_MASK        (0xFFFFFFFFu)
#define CSL_NAND_CE2ALE_ADDR_SHIFT       (0x00000000u)
#define CSL_NAND_CE2ALE_ADDR_RESETVAL    (0x00000000u)

#define CSL_NAND_CE2ALE_RESETVAL         (0x00000000u)

/* CE2CLE */

#define CSL_NAND_CE2CLE_ADDR_MASK        (0xFFFFFFFFu)
#define CSL_NAND_CE2CLE_ADDR_SHIFT       (0x00000000u)
#define CSL_NAND_CE2CLE_ADDR_RESETVAL    (0x00000000u)

#define CSL_NAND_CE2CLE_RESETVAL         (0x00000000u)

/* CE3DATA */

#define CSL_NAND_CE3DATA_ADDR_MASK       (0xFFFFFFFFu)
#define CSL_NAND_CE3DATA_ADDR_SHIFT      (0x00000000u)
#define CSL_NAND_CE3DATA_ADDR_RESETVAL   (0x00000000u)

#define CSL_NAND_CE3DATA_RESETVAL        (0x00000000u)

/* CE3ALE */

#define CSL_NAND_CE3ALE_ADDR_MASK        (0xFFFFFFFFu)
#define CSL_NAND_CE3ALE_ADDR_SHIFT       (0x00000000u)
#define CSL_NAND_CE3ALE_ADDR_RESETVAL    (0x00000000u)

#define CSL_NAND_CE3ALE_RESETVAL         (0x00000000u)

/* CE3CLE */

#define CSL_NAND_CE3CLE_ADDR_MASK        (0xFFFFFFFFu)
#define CSL_NAND_CE3CLE_ADDR_SHIFT       (0x00000000u)
#define CSL_NAND_CE3CLE_ADDR_RESETVAL    (0x00000000u)

#define CSL_NAND_CE3CLE_RESETVAL         (0x00000000u)

#endif