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📄 csl_nandaux.h

📁 TI达芬奇dm644x各硬件模块测试代码
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/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */ 

/** @file csl_nandAux.h
 *
 * @brief  API Auxilary header file for NAND CSL.
 *
 * Description
 *    - The decribes the definitions of the inline functions
 *
 *  Path: \\(CSLPATH)\\ipmodules\\nfc\\src
 *
 */ 

/*  ===========================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in 
 *   the license agreement under which this software has been supplied.
 *   ==========================================================================
 */
 
/* ============================================================================
 *  Revision History
 *  ===============
 *  03-Sep-2004 Nsr Added inline functions for query commands also.
 *  03-Sep-2004 Nsr File Created from CSL_nandHwControl.c and 
 *                  CSL_nandGetHwStatus.c.
 *
 * ============================================================================
 */

#ifndef _CSL_NANDAUX_H_
#define _CSL_NANDAUX_H_

#include<csl_nand.h>

#ifdef __cplusplus
extern "C" {
#endif

/**
 *  Control Command Functions of nand.
 */

/** ===========================================================================
 *   @n@b CSL_nandWrEnable
 *
 *   @b Description
 *   @n This function enables the NAND Wait rise interrupt capability.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance
            arg              this is the veriable of type Uint16.
            
     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim

        CSL_nandWrEnable (hNand,arg);

     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_nandWrEnable (
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle        hNand,
    Uint16                arg
)
{
    CSL_FINS(hNand->regs->NIMSR, NAND_NIMSR_WRMSET, arg);
}


/** ===========================================================================
 *   @n@b CSL_nandWrDisable
 *
 *   @b Description
 *   @n This function disables the NAND Wait rise interrupt capability.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance
            arg              this is the veriable of type Uint16.

     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim

        CSL_nandWrDisable (hNand,arg);

     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_nandWrDisable (
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle        hNand,
    Uint16                arg
)
{
    CSL_FINS(hNand->regs->NIMCR, NAND_NIMCR_WRMCLR,arg);
}


/** ===========================================================================
 *   @n@b CSL_nandLtEnable
 *
 *   @b Description
 *   @n This function enables the NAND Line Trap interrupt capability.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance

     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim

        CSL_nandLtEnable (hNand);

     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_nandLtEnable (
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle        hNand
)
{
    CSL_FINS(hNand->regs->NIMSR, NAND_NIMSR_LTMSET,TRUE);
}


/** ===========================================================================
 *   @n@b CSL_nandLtDisable
 *
 *   @b Description
 *   @n This function disables the NAND Line Trap interrupt capability.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance

     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim

        CSL_nandLtDisable (hNand);

     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_nandLtDisable (
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle        hNand
)
{
    CSL_FINS(hNand->regs->NIMCR, NAND_NIMCR_LTMCLR,TRUE);
}


/** ===========================================================================
 *   @n@b CSL_nandAtenable
 *
 *   @b Description
 *   @n This function enables the NAND Asynchronous Time Out interrupt 
 *      capability.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance

     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim

        CSL_nandAtEnable (hNand);

     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_nandAtEnable (
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle        hNand
)
{
    CSL_FINS(hNand->regs->NIMSR, NAND_NIMSR_ATMSET,TRUE);
}


/** ===========================================================================
 *   @n@b CSL_nandAtDisable
 *
 *   @b Description
 *   @n This function disables the NAND Asynchronous Time Out interrupt 
 *      capability.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance

     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim

        CSL_nandAtDisable (hNand);

     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_nandAtDisable (
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle        hNand
)
{
    CSL_FINS(hNand->regs->NIMCR, NAND_NIMCR_ATMCLR,TRUE);
}


/** ===========================================================================
 *   @n@b CSL_nandCs5EccStart
 *
 *   @b Description
 *   @n This function sets the NAND Chip Select 5 Ecc Start bit.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance

     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim

        CSL_nandCs5EccStart (hNand);

     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_nandCs5EccStart (
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle        hNand
)
{
    CSL_FINS(hNand->regs->NANDFCR, NAND_NANDFCR_CS5ECC, TRUE);
}


/** ===========================================================================
 *   @n@b CSL_nandCs4EccStart
 *
 *   @b Description
 *   @n This function sets the NAND Chip Select 4 Ecc Start bit.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance

     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim

        CSL_nandCs4EccStart (hNand);

     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_nandCs4EccStart (
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle        hNand
)
{
    CSL_FINS(hNand->regs->NANDFCR, NAND_NANDFCR_CS4ECC, TRUE);
}


/** ===========================================================================
 *   @n@b CSL_nandCs3EccStart
 *
 *   @b Description
 *   @n This function sets the NAND Chip Select 3 Ecc Start bit.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance

     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim

        CSL_nandCs5EccStart (hNand);

     @endverbatim
 * ===========================================================================
 */
CSL_IDEF_INLINE
void CSL_nandCs3EccStart (
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call
     */
    CSL_NandHandle        hNand
)
{
    CSL_FINS(hNand->regs->NANDFCR, NAND_NANDFCR_CS3ECC, TRUE);
}


/** ===========================================================================
 *   @n@b CSL_nandCs2EccStart
 *
 *   @b Description
 *   @n This function sets the NAND Chip Select 2 Ecc Start bit.
 *
 *   @b Arguments
 *   @verbatim

            hNand            Handle to NAND instance

     @endverbatim
 *
 *   <b> Return Value </b>  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n None
 *
 *   @b Modifies
 *   @n  None
 *

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