cslr_emif.h

TI达芬奇dm644x各硬件模块测试代码

#define CSL_EMIF_NANDF1ECC_P2O_MASK      (0x00020000u)
#define CSL_EMIF_NANDF1ECC_P2O_SHIFT     (0x00000011u)
#define CSL_EMIF_NANDF1ECC_P2O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P1O_MASK      (0x00010000u)
#define CSL_EMIF_NANDF1ECC_P1O_SHIFT     (0x00000010u)
#define CSL_EMIF_NANDF1ECC_P1O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P2048E_MASK   (0x00000800u)
#define CSL_EMIF_NANDF1ECC_P2048E_SHIFT  (0x0000000Bu)
#define CSL_EMIF_NANDF1ECC_P2048E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P1024E_MASK   (0x00000400u)
#define CSL_EMIF_NANDF1ECC_P1024E_SHIFT  (0x0000000Au)
#define CSL_EMIF_NANDF1ECC_P1024E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P512E_MASK    (0x00000200u)
#define CSL_EMIF_NANDF1ECC_P512E_SHIFT   (0x00000009u)
#define CSL_EMIF_NANDF1ECC_P512E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P256E_MASK    (0x00000100u)
#define CSL_EMIF_NANDF1ECC_P256E_SHIFT   (0x00000008u)
#define CSL_EMIF_NANDF1ECC_P256E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P128E_MASK    (0x00000080u)
#define CSL_EMIF_NANDF1ECC_P128E_SHIFT   (0x00000007u)
#define CSL_EMIF_NANDF1ECC_P128E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P64E_MASK     (0x00000040u)
#define CSL_EMIF_NANDF1ECC_P64E_SHIFT    (0x00000006u)
#define CSL_EMIF_NANDF1ECC_P64E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P32E_MASK     (0x00000020u)
#define CSL_EMIF_NANDF1ECC_P32E_SHIFT    (0x00000005u)
#define CSL_EMIF_NANDF1ECC_P32E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P16E_MASK     (0x00000010u)
#define CSL_EMIF_NANDF1ECC_P16E_SHIFT    (0x00000004u)
#define CSL_EMIF_NANDF1ECC_P16E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P8E_MASK      (0x00000008u)
#define CSL_EMIF_NANDF1ECC_P8E_SHIFT     (0x00000003u)
#define CSL_EMIF_NANDF1ECC_P8E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P4E_MASK      (0x00000004u)
#define CSL_EMIF_NANDF1ECC_P4E_SHIFT     (0x00000002u)
#define CSL_EMIF_NANDF1ECC_P4E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P2E_MASK      (0x00000002u)
#define CSL_EMIF_NANDF1ECC_P2E_SHIFT     (0x00000001u)
#define CSL_EMIF_NANDF1ECC_P2E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P1E_MASK      (0x00000001u)
#define CSL_EMIF_NANDF1ECC_P1E_SHIFT     (0x00000000u)
#define CSL_EMIF_NANDF1ECC_P1E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_RESETVAL      (0x00000000u)

/* NANDF2ECC */

#define CSL_EMIF_NANDF2ECC_P2048O_MASK   (0x08000000u)
#define CSL_EMIF_NANDF2ECC_P2048O_SHIFT  (0x0000001Bu)
#define CSL_EMIF_NANDF2ECC_P2048O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P1024O_MASK   (0x04000000u)
#define CSL_EMIF_NANDF2ECC_P1024O_SHIFT  (0x0000001Au)
#define CSL_EMIF_NANDF2ECC_P1024O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P512O_MASK    (0x02000000u)
#define CSL_EMIF_NANDF2ECC_P512O_SHIFT   (0x00000019u)
#define CSL_EMIF_NANDF2ECC_P512O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P256O_MASK    (0x01000000u)
#define CSL_EMIF_NANDF2ECC_P256O_SHIFT   (0x00000018u)
#define CSL_EMIF_NANDF2ECC_P256O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P128O_MASK    (0x00800000u)
#define CSL_EMIF_NANDF2ECC_P128O_SHIFT   (0x00000017u)
#define CSL_EMIF_NANDF2ECC_P128O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P64O_MASK     (0x00400000u)
#define CSL_EMIF_NANDF2ECC_P64O_SHIFT    (0x00000016u)
#define CSL_EMIF_NANDF2ECC_P64O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P32O_MASK     (0x00200000u)
#define CSL_EMIF_NANDF2ECC_P32O_SHIFT    (0x00000015u)
#define CSL_EMIF_NANDF2ECC_P32O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P16O_MASK     (0x00100000u)
#define CSL_EMIF_NANDF2ECC_P16O_SHIFT    (0x00000014u)
#define CSL_EMIF_NANDF2ECC_P16O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P8O_MASK      (0x00080000u)
#define CSL_EMIF_NANDF2ECC_P8O_SHIFT     (0x00000013u)
#define CSL_EMIF_NANDF2ECC_P8O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P4O_MASK      (0x00040000u)
#define CSL_EMIF_NANDF2ECC_P4O_SHIFT     (0x00000012u)
#define CSL_EMIF_NANDF2ECC_P4O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P2O_MASK      (0x00020000u)
#define CSL_EMIF_NANDF2ECC_P2O_SHIFT     (0x00000011u)
#define CSL_EMIF_NANDF2ECC_P2O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P1O_MASK      (0x00010000u)
#define CSL_EMIF_NANDF2ECC_P1O_SHIFT     (0x00000010u)
#define CSL_EMIF_NANDF2ECC_P1O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P2048E_MASK   (0x00000800u)
#define CSL_EMIF_NANDF2ECC_P2048E_SHIFT  (0x0000000Bu)
#define CSL_EMIF_NANDF2ECC_P2048E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P1024E_MASK   (0x00000400u)
#define CSL_EMIF_NANDF2ECC_P1024E_SHIFT  (0x0000000Au)
#define CSL_EMIF_NANDF2ECC_P1024E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P512E_MASK    (0x00000200u)
#define CSL_EMIF_NANDF2ECC_P512E_SHIFT   (0x00000009u)
#define CSL_EMIF_NANDF2ECC_P512E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P256E_MASK    (0x00000100u)
#define CSL_EMIF_NANDF2ECC_P256E_SHIFT   (0x00000008u)
#define CSL_EMIF_NANDF2ECC_P256E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P128E_MASK    (0x00000080u)
#define CSL_EMIF_NANDF2ECC_P128E_SHIFT   (0x00000007u)
#define CSL_EMIF_NANDF2ECC_P128E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P64E_MASK     (0x00000040u)
#define CSL_EMIF_NANDF2ECC_P64E_SHIFT    (0x00000006u)
#define CSL_EMIF_NANDF2ECC_P64E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P32E_MASK     (0x00000020u)
#define CSL_EMIF_NANDF2ECC_P32E_SHIFT    (0x00000005u)
#define CSL_EMIF_NANDF2ECC_P32E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P16E_MASK     (0x00000010u)
#define CSL_EMIF_NANDF2ECC_P16E_SHIFT    (0x00000004u)
#define CSL_EMIF_NANDF2ECC_P16E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P8E_MASK      (0x00000008u)
#define CSL_EMIF_NANDF2ECC_P8E_SHIFT     (0x00000003u)
#define CSL_EMIF_NANDF2ECC_P8E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P4E_MASK      (0x00000004u)
#define CSL_EMIF_NANDF2ECC_P4E_SHIFT     (0x00000002u)
#define CSL_EMIF_NANDF2ECC_P4E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P2E_MASK      (0x00000002u)
#define CSL_EMIF_NANDF2ECC_P2E_SHIFT     (0x00000001u)
#define CSL_EMIF_NANDF2ECC_P2E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF2ECC_P1E_MASK      (0x00000001u)
#define CSL_EMIF_NANDF2ECC_P1E_SHIFT     (0x00000000u)
#define CSL_EMIF_NANDF2ECC_P1E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF2ECC_RESETVAL      (0x00000000u)

/* NANDF3ECC */

#define CSL_EMIF_NANDF3ECC_P2048O_MASK   (0x08000000u)
#define CSL_EMIF_NANDF3ECC_P2048O_SHIFT  (0x0000001Bu)
#define CSL_EMIF_NANDF3ECC_P2048O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P1024O_MASK   (0x04000000u)
#define CSL_EMIF_NANDF3ECC_P1024O_SHIFT  (0x0000001Au)
#define CSL_EMIF_NANDF3ECC_P1024O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P512O_MASK    (0x02000000u)
#define CSL_EMIF_NANDF3ECC_P512O_SHIFT   (0x00000019u)
#define CSL_EMIF_NANDF3ECC_P512O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P256O_MASK    (0x01000000u)
#define CSL_EMIF_NANDF3ECC_P256O_SHIFT   (0x00000018u)
#define CSL_EMIF_NANDF3ECC_P256O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P128O_MASK    (0x00800000u)
#define CSL_EMIF_NANDF3ECC_P128O_SHIFT   (0x00000017u)
#define CSL_EMIF_NANDF3ECC_P128O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P64O_MASK     (0x00400000u)
#define CSL_EMIF_NANDF3ECC_P64O_SHIFT    (0x00000016u)
#define CSL_EMIF_NANDF3ECC_P64O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P32O_MASK     (0x00200000u)
#define CSL_EMIF_NANDF3ECC_P32O_SHIFT    (0x00000015u)
#define CSL_EMIF_NANDF3ECC_P32O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P16O_MASK     (0x00100000u)
#define CSL_EMIF_NANDF3ECC_P16O_SHIFT    (0x00000014u)
#define CSL_EMIF_NANDF3ECC_P16O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P8O_MASK      (0x00080000u)
#define CSL_EMIF_NANDF3ECC_P8O_SHIFT     (0x00000013u)
#define CSL_EMIF_NANDF3ECC_P8O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P4O_MASK      (0x00040000u)
#define CSL_EMIF_NANDF3ECC_P4O_SHIFT     (0x00000012u)
#define CSL_EMIF_NANDF3ECC_P4O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P2O_MASK      (0x00020000u)
#define CSL_EMIF_NANDF3ECC_P2O_SHIFT     (0x00000011u)
#define CSL_EMIF_NANDF3ECC_P2O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P1O_MASK      (0x00010000u)
#define CSL_EMIF_NANDF3ECC_P1O_SHIFT     (0x00000010u)
#define CSL_EMIF_NANDF3ECC_P1O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P2048E_MASK   (0x00000800u)
#define CSL_EMIF_NANDF3ECC_P2048E_SHIFT  (0x0000000Bu)
#define CSL_EMIF_NANDF3ECC_P2048E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P1024E_MASK   (0x00000400u)
#define CSL_EMIF_NANDF3ECC_P1024E_SHIFT  (0x0000000Au)
#define CSL_EMIF_NANDF3ECC_P1024E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P512E_MASK    (0x00000200u)
#define CSL_EMIF_NANDF3ECC_P512E_SHIFT   (0x00000009u)
#define CSL_EMIF_NANDF3ECC_P512E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P256E_MASK    (0x00000100u)
#define CSL_EMIF_NANDF3ECC_P256E_SHIFT   (0x00000008u)
#define CSL_EMIF_NANDF3ECC_P256E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P128E_MASK    (0x00000080u)
#define CSL_EMIF_NANDF3ECC_P128E_SHIFT   (0x00000007u)
#define CSL_EMIF_NANDF3ECC_P128E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P64E_MASK     (0x00000040u)
#define CSL_EMIF_NANDF3ECC_P64E_SHIFT    (0x00000006u)
#define CSL_EMIF_NANDF3ECC_P64E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P32E_MASK     (0x00000020u)
#define CSL_EMIF_NANDF3ECC_P32E_SHIFT    (0x00000005u)
#define CSL_EMIF_NANDF3ECC_P32E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P16E_MASK     (0x00000010u)
#define CSL_EMIF_NANDF3ECC_P16E_SHIFT    (0x00000004u)
#define CSL_EMIF_NANDF3ECC_P16E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P8E_MASK      (0x00000008u)
#define CSL_EMIF_NANDF3ECC_P8E_SHIFT     (0x00000003u)
#define CSL_EMIF_NANDF3ECC_P8E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P4E_MASK      (0x00000004u)
#define CSL_EMIF_NANDF3ECC_P4E_SHIFT     (0x00000002u)
#define CSL_EMIF_NANDF3ECC_P4E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P2E_MASK      (0x00000002u)
#define CSL_EMIF_NANDF3ECC_P2E_SHIFT     (0x00000001u)
#define CSL_EMIF_NANDF3ECC_P2E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF3ECC_P1E_MASK      (0x00000001u)
#define CSL_EMIF_NANDF3ECC_P1E_SHIFT     (0x00000000u)
#define CSL_EMIF_NANDF3ECC_P1E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF3ECC_RESETVAL      (0x00000000u)

/* NANDF4ECC */

#define CSL_EMIF_NANDF4ECC_P2048O_MASK   (0x08000000u)
#define CSL_EMIF_NANDF4ECC_P2048O_SHIFT  (0x0000001Bu)
#define CSL_EMIF_NANDF4ECC_P2048O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P1024O_MASK   (0x04000000u)
#define CSL_EMIF_NANDF4ECC_P1024O_SHIFT  (0x0000001Au)
#define CSL_EMIF_NANDF4ECC_P1024O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P512O_MASK    (0x02000000u)
#define CSL_EMIF_NANDF4ECC_P512O_SHIFT   (0x00000019u)
#define CSL_EMIF_NANDF4ECC_P512O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P256O_MASK    (0x01000000u)
#define CSL_EMIF_NANDF4ECC_P256O_SHIFT   (0x00000018u)
#define CSL_EMIF_NANDF4ECC_P256O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P128O_MASK    (0x00800000u)
#define CSL_EMIF_NANDF4ECC_P128O_SHIFT   (0x00000017u)
#define CSL_EMIF_NANDF4ECC_P128O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P64O_MASK     (0x00400000u)
#define CSL_EMIF_NANDF4ECC_P64O_SHIFT    (0x00000016u)
#define CSL_EMIF_NANDF4ECC_P64O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P32O_MASK     (0x00200000u)
#define CSL_EMIF_NANDF4ECC_P32O_SHIFT    (0x00000015u)
#define CSL_EMIF_NANDF4ECC_P32O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P16O_MASK     (0x00100000u)
#define CSL_EMIF_NANDF4ECC_P16O_SHIFT    (0x00000014u)
#define CSL_EMIF_NANDF4ECC_P16O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P8O_MASK      (0x00080000u)
#define CSL_EMIF_NANDF4ECC_P8O_SHIFT     (0x00000013u)
#define CSL_EMIF_NANDF4ECC_P8O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P4O_MASK      (0x00040000u)
#define CSL_EMIF_NANDF4ECC_P4O_SHIFT     (0x00000012u)
#define CSL_EMIF_NANDF4ECC_P4O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P2O_MASK      (0x00020000u)
#define CSL_EMIF_NANDF4ECC_P2O_SHIFT     (0x00000011u)
#define CSL_EMIF_NANDF4ECC_P2O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P1O_MASK      (0x00010000u)
#define CSL_EMIF_NANDF4ECC_P1O_SHIFT     (0x00000010u)
#define CSL_EMIF_NANDF4ECC_P1O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P2048E_MASK   (0x00000800u)
#define CSL_EMIF_NANDF4ECC_P2048E_SHIFT  (0x0000000Bu)
#define CSL_EMIF_NANDF4ECC_P2048E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P1024E_MASK   (0x00000400u)
#define CSL_EMIF_NANDF4ECC_P1024E_SHIFT  (0x0000000Au)
#define CSL_EMIF_NANDF4ECC_P1024E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P512E_MASK    (0x00000200u)
#define CSL_EMIF_NANDF4ECC_P512E_SHIFT   (0x00000009u)
#define CSL_EMIF_NANDF4ECC_P512E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P256E_MASK    (0x00000100u)
#define CSL_EMIF_NANDF4ECC_P256E_SHIFT   (0x00000008u)
#define CSL_EMIF_NANDF4ECC_P256E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P128E_MASK    (0x00000080u)
#define CSL_EMIF_NANDF4ECC_P128E_SHIFT   (0x00000007u)
#define CSL_EMIF_NANDF4ECC_P128E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P64E_MASK     (0x00000040u)
#define CSL_EMIF_NANDF4ECC_P64E_SHIFT    (0x00000006u)
#define CSL_EMIF_NANDF4ECC_P64E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P32E_MASK     (0x00000020u)
#define CSL_EMIF_NANDF4ECC_P32E_SHIFT    (0x00000005u)
#define CSL_EMIF_NANDF4ECC_P32E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P16E_MASK     (0x00000010u)
#define CSL_EMIF_NANDF4ECC_P16E_SHIFT    (0x00000004u)
#define CSL_EMIF_NANDF4ECC_P16E_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P8E_MASK      (0x00000008u)
#define CSL_EMIF_NANDF4ECC_P8E_SHIFT     (0x00000003u)
#define CSL_EMIF_NANDF4ECC_P8E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P4E_MASK      (0x00000004u)
#define CSL_EMIF_NANDF4ECC_P4E_SHIFT     (0x00000002u)
#define CSL_EMIF_NANDF4ECC_P4E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P2E_MASK      (0x00000002u)
#define CSL_EMIF_NANDF4ECC_P2E_SHIFT     (0x00000001u)
#define CSL_EMIF_NANDF4ECC_P2E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF4ECC_P1E_MASK      (0x00000001u)
#define CSL_EMIF_NANDF4ECC_P1E_SHIFT     (0x00000000u)
#define CSL_EMIF_NANDF4ECC_P1E_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF4ECC_RESETVAL      (0x00000000u)

#endif