cslr_emif.h

TI达芬奇dm644x各硬件模块测试代码

#define CSL_EMIF_AB3CR_ASIZE_MASK        (0x00000003u)
#define CSL_EMIF_AB3CR_ASIZE_SHIFT       (0x00000000u)
#define CSL_EMIF_AB3CR_ASIZE_RESETVAL    (0x00000001u)

/*----ASIZE Tokens----*/
#define CSL_EMIF_AB3CR_ASIZE_ASIZE_8BITS (0x00000000u)
#define CSL_EMIF_AB3CR_ASIZE_ASIZE_16BITS (0x00000001u)

#define CSL_EMIF_AB3CR_RESETVAL          (0x3FFFFFFDu)

/* AB4CR */

#define CSL_EMIF_AB4CR_SS_MASK           (0x80000000u)
#define CSL_EMIF_AB4CR_SS_SHIFT          (0x0000001Fu)
#define CSL_EMIF_AB4CR_SS_RESETVAL       (0x00000000u)

#define CSL_EMIF_AB4CR_EW_MASK           (0x40000000u)
#define CSL_EMIF_AB4CR_EW_SHIFT          (0x0000001Eu)
#define CSL_EMIF_AB4CR_EW_RESETVAL       (0x00000000u)

#define CSL_EMIF_AB4CR_W_SETUP_MASK      (0x3C000000u)
#define CSL_EMIF_AB4CR_W_SETUP_SHIFT     (0x0000001Au)
#define CSL_EMIF_AB4CR_W_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_EMIF_AB4CR_W_STROBE_MASK     (0x03F00000u)
#define CSL_EMIF_AB4CR_W_STROBE_SHIFT    (0x00000014u)
#define CSL_EMIF_AB4CR_W_STROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF_AB4CR_W_HOLD_MASK       (0x000E0000u)
#define CSL_EMIF_AB4CR_W_HOLD_SHIFT      (0x00000011u)
#define CSL_EMIF_AB4CR_W_HOLD_RESETVAL   (0x00000007u)

#define CSL_EMIF_AB4CR_R_SETUP_MASK      (0x0001E000u)
#define CSL_EMIF_AB4CR_R_SETUP_SHIFT     (0x0000000Du)
#define CSL_EMIF_AB4CR_R_SETUP_RESETVAL  (0x0000000Fu)

#define CSL_EMIF_AB4CR_R_STROBE_MASK     (0x00001F80u)
#define CSL_EMIF_AB4CR_R_STROBE_SHIFT    (0x00000007u)
#define CSL_EMIF_AB4CR_R_STROBE_RESETVAL (0x0000003Fu)

#define CSL_EMIF_AB4CR_R_HOLD_MASK       (0x00000070u)
#define CSL_EMIF_AB4CR_R_HOLD_SHIFT      (0x00000004u)
#define CSL_EMIF_AB4CR_R_HOLD_RESETVAL   (0x00000007u)

#define CSL_EMIF_AB4CR_TA_MASK           (0x0000000Cu)
#define CSL_EMIF_AB4CR_TA_SHIFT          (0x00000002u)
#define CSL_EMIF_AB4CR_TA_RESETVAL       (0x00000003u)

#define CSL_EMIF_AB4CR_ASIZE_MASK        (0x00000003u)
#define CSL_EMIF_AB4CR_ASIZE_SHIFT       (0x00000000u)
#define CSL_EMIF_AB4CR_ASIZE_RESETVAL    (0x00000001u)

/*----ASIZE Tokens----*/
#define CSL_EMIF_AB4CR_ASIZE_ASIZE_8BITS (0x00000000u)
#define CSL_EMIF_AB4CR_ASIZE_ASIZE_16BITS (0x00000001u)

#define CSL_EMIF_AB4CR_RESETVAL          (0x3FFFFFFDu)

/* SDTIMR */

#define CSL_EMIF_SDTIMR_T_RFC_MASK       (0xF8000000u)
#define CSL_EMIF_SDTIMR_T_RFC_SHIFT      (0x0000001Bu)
#define CSL_EMIF_SDTIMR_T_RFC_RESETVAL   (0x00000000u)

#define CSL_EMIF_SDTIMR_T_RP_MASK        (0x07000000u)
#define CSL_EMIF_SDTIMR_T_RP_SHIFT       (0x00000018u)
#define CSL_EMIF_SDTIMR_T_RP_RESETVAL    (0x00000000u)

#define CSL_EMIF_SDTIMR_T_RCD_MASK       (0x00700000u)
#define CSL_EMIF_SDTIMR_T_RCD_SHIFT      (0x00000014u)
#define CSL_EMIF_SDTIMR_T_RCD_RESETVAL   (0x00000000u)

#define CSL_EMIF_SDTIMR_T_WR_MASK        (0x00070000u)
#define CSL_EMIF_SDTIMR_T_WR_SHIFT       (0x00000010u)
#define CSL_EMIF_SDTIMR_T_WR_RESETVAL    (0x00000000u)

#define CSL_EMIF_SDTIMR_T_RAS_MASK       (0x0000F000u)
#define CSL_EMIF_SDTIMR_T_RAS_SHIFT      (0x0000000Cu)
#define CSL_EMIF_SDTIMR_T_RAS_RESETVAL   (0x00000004u)

#define CSL_EMIF_SDTIMR_T_RC_MASK        (0x00000F00u)
#define CSL_EMIF_SDTIMR_T_RC_SHIFT       (0x00000008u)
#define CSL_EMIF_SDTIMR_T_RC_RESETVAL    (0x00000000u)

#define CSL_EMIF_SDTIMR_T_RRD_MASK       (0x00000070u)
#define CSL_EMIF_SDTIMR_T_RRD_SHIFT      (0x00000004u)
#define CSL_EMIF_SDTIMR_T_RRD_RESETVAL   (0x00000000u)

#define CSL_EMIF_SDTIMR_RESETVAL         (0x00004000u)

/* DDRSR */

#define CSL_EMIF_DDRSR_PHYDLLRDY_MASK    (0x00000008u)
#define CSL_EMIF_DDRSR_PHYDLLRDY_SHIFT   (0x00000003u)
#define CSL_EMIF_DDRSR_PHYDLLRDY_RESETVAL (0x00000000u)

#define CSL_EMIF_DDRSR_TRPHYCS1_MASK     (0x00000004u)
#define CSL_EMIF_DDRSR_TRPHYCS1_SHIFT    (0x00000002u)
#define CSL_EMIF_DDRSR_TRPHYCS1_RESETVAL (0x00000000u)

#define CSL_EMIF_DDRSR_TRPHYCS0_MASK     (0x00000002u)
#define CSL_EMIF_DDRSR_TRPHYCS0_SHIFT    (0x00000001u)
#define CSL_EMIF_DDRSR_TRPHYCS0_RESETVAL (0x00000000u)

#define CSL_EMIF_DDRSR_DDR_MASK          (0x00000001u)
#define CSL_EMIF_DDRSR_DDR_SHIFT         (0x00000000u)
#define CSL_EMIF_DDRSR_DDR_RESETVAL      (0x00000000u)

#define CSL_EMIF_DDRSR_RESETVAL          (0x00000000u)

/* DDRPHYCR */

#define CSL_EMIF_DDRPHYCR_TAPV_EN_MASK   (0x00400000u)
#define CSL_EMIF_DDRPHYCR_TAPV_EN_SHIFT  (0x00000016u)
#define CSL_EMIF_DDRPHYCR_TAPV_EN_RESETVAL (0x00000001u)

#define CSL_EMIF_DDRPHYCR_TAPV_MASK      (0x003F0000u)
#define CSL_EMIF_DDRPHYCR_TAPV_SHIFT     (0x00000010u)
#define CSL_EMIF_DDRPHYCR_TAPV_RESETVAL  (0x0000003Fu)

#define CSL_EMIF_DDRPHYCR_TRAIN_MASK     (0x0000FFFFu)
#define CSL_EMIF_DDRPHYCR_TRAIN_SHIFT    (0x00000000u)
#define CSL_EMIF_DDRPHYCR_TRAIN_RESETVAL (0x0000FFFFu)

#define CSL_EMIF_DDRPHYCR_RESETVAL       (0x007FFFFFu)

/* DDRPHYSR */

#define CSL_EMIF_DDRPHYSR_TLDQ3SEL_MASK  (0x40000000u)
#define CSL_EMIF_DDRPHYSR_TLDQ3SEL_SHIFT (0x0000001Eu)
#define CSL_EMIF_DDRPHYSR_TLDQ3SEL_RESETVAL (0x00000001u)

#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ3_MASK (0x3F000000u)
#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ3_SHIFT (0x00000018u)
#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ3_RESETVAL (0x0000001Fu)

#define CSL_EMIF_DDRPHYSR_TLDQ2SEL_MASK  (0x00400000u)
#define CSL_EMIF_DDRPHYSR_TLDQ2SEL_SHIFT (0x00000016u)
#define CSL_EMIF_DDRPHYSR_TLDQ2SEL_RESETVAL (0x00000001u)

#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ2_MASK (0x003F0000u)
#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ2_SHIFT (0x00000010u)
#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ2_RESETVAL (0x0000001Fu)

#define CSL_EMIF_DDRPHYSR_TLDQ1SEL_MASK  (0x00004000u)
#define CSL_EMIF_DDRPHYSR_TLDQ1SEL_SHIFT (0x0000000Eu)
#define CSL_EMIF_DDRPHYSR_TLDQ1SEL_RESETVAL (0x00000001u)

#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ1_MASK (0x00003F00u)
#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ1_SHIFT (0x00000008u)
#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ1_RESETVAL (0x0000001Fu)

#define CSL_EMIF_DDRPHYSR_TLDQ0SEL_MASK  (0x00000040u)
#define CSL_EMIF_DDRPHYSR_TLDQ0SEL_SHIFT (0x00000006u)
#define CSL_EMIF_DDRPHYSR_TLDQ0SEL_RESETVAL (0x00000001u)

#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ0_MASK (0x0000003Fu)
#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ0_SHIFT (0x00000000u)
#define CSL_EMIF_DDRPHYSR_TAPLVL1DQ0_RESETVAL (0x0000001Fu)

#define CSL_EMIF_DDRPHYSR_RESETVAL       (0x5F5F5F5Fu)

/* TOTAR */

#define CSL_EMIF_TOTAR_TA_MASK           (0xFFFFFFFFu)
#define CSL_EMIF_TOTAR_TA_SHIFT          (0x00000000u)
#define CSL_EMIF_TOTAR_TA_RESETVAL       (0x00000000u)

#define CSL_EMIF_TOTAR_RESETVAL          (0x00000000u)

/* TOTACTR */

#define CSL_EMIF_TOTACTR_TACT_MASK       (0xFFFFFFFFu)
#define CSL_EMIF_TOTACTR_TACT_SHIFT      (0x00000000u)
#define CSL_EMIF_TOTACTR_TACT_RESETVAL   (0x00000000u)

#define CSL_EMIF_TOTACTR_RESETVAL        (0x00000000u)

/* DDRPHYID_REV */

#define CSL_EMIF_DDRPHYID_REV_DDRPHYID_REV_MASK (0xFFFFFFFFu)
#define CSL_EMIF_DDRPHYID_REV_DDRPHYID_REV_SHIFT (0x00000000u)
#define CSL_EMIF_DDRPHYID_REV_DDRPHYID_REV_RESETVAL (0x00000000u)

#define CSL_EMIF_DDRPHYID_REV_RESETVAL   (0x00000000u)

/* SDSRETR */

#define CSL_EMIF_SDSRETR_T_XS_MASK       (0x0000001Fu)
#define CSL_EMIF_SDSRETR_T_XS_SHIFT      (0x00000000u)
#define CSL_EMIF_SDSRETR_T_XS_RESETVAL   (0x00000000u)

#define CSL_EMIF_SDSRETR_RESETVAL        (0x00000000u)

/* EIRR */

#define CSL_EMIF_EIRR_WR_MASK            (0x0000003Cu)
#define CSL_EMIF_EIRR_WR_SHIFT           (0x00000002u)
#define CSL_EMIF_EIRR_WR_RESETVAL        (0x00000000u)

#define CSL_EMIF_EIRR_LT_MASK            (0x00000002u)
#define CSL_EMIF_EIRR_LT_SHIFT           (0x00000001u)
#define CSL_EMIF_EIRR_LT_RESETVAL        (0x00000000u)

#define CSL_EMIF_EIRR_AT_MASK            (0x00000001u)
#define CSL_EMIF_EIRR_AT_SHIFT           (0x00000000u)
#define CSL_EMIF_EIRR_AT_RESETVAL        (0x00000000u)

#define CSL_EMIF_EIRR_RESETVAL           (0x00000000u)

/* EIMR */

#define CSL_EMIF_EIMR_WRM_MASK           (0x0000003Cu)
#define CSL_EMIF_EIMR_WRM_SHIFT          (0x00000002u)
#define CSL_EMIF_EIMR_WRM_RESETVAL       (0x00000000u)

#define CSL_EMIF_EIMR_LTM_MASK           (0x00000002u)
#define CSL_EMIF_EIMR_LTM_SHIFT          (0x00000001u)
#define CSL_EMIF_EIMR_LTM_RESETVAL       (0x00000000u)

#define CSL_EMIF_EIMR_ATM_MASK           (0x00000001u)
#define CSL_EMIF_EIMR_ATM_SHIFT          (0x00000000u)
#define CSL_EMIF_EIMR_ATM_RESETVAL       (0x00000000u)

#define CSL_EMIF_EIMR_RESETVAL           (0x00000000u)

/* EIMSR */

#define CSL_EMIF_EIMSR_WRMSET_MASK       (0x0000003Cu)
#define CSL_EMIF_EIMSR_WRMSET_SHIFT      (0x00000002u)
#define CSL_EMIF_EIMSR_WRMSET_RESETVAL   (0x00000000u)

#define CSL_EMIF_EIMSR_LTMSET_MASK       (0x00000002u)
#define CSL_EMIF_EIMSR_LTMSET_SHIFT      (0x00000001u)
#define CSL_EMIF_EIMSR_LTMSET_RESETVAL   (0x00000000u)

#define CSL_EMIF_EIMSR_ATMSET_MASK       (0x00000001u)
#define CSL_EMIF_EIMSR_ATMSET_SHIFT      (0x00000000u)
#define CSL_EMIF_EIMSR_ATMSET_RESETVAL   (0x00000000u)

#define CSL_EMIF_EIMSR_RESETVAL          (0x00000000u)

/* EIMCR */

#define CSL_EMIF_EIMCR_WRMCLR_MASK       (0x0000003Cu)
#define CSL_EMIF_EIMCR_WRMCLR_SHIFT      (0x00000002u)
#define CSL_EMIF_EIMCR_WRMCLR_RESETVAL   (0x00000000u)

#define CSL_EMIF_EIMCR_LTMCLR_MASK       (0x00000002u)
#define CSL_EMIF_EIMCR_LTMCLR_SHIFT      (0x00000001u)
#define CSL_EMIF_EIMCR_LTMCLR_RESETVAL   (0x00000000u)

#define CSL_EMIF_EIMCR_ATMCLR_MASK       (0x00000001u)
#define CSL_EMIF_EIMCR_ATMCLR_SHIFT      (0x00000000u)
#define CSL_EMIF_EIMCR_ATMCLR_RESETVAL   (0x00000000u)

#define CSL_EMIF_EIMCR_RESETVAL          (0x00000000u)

/* IOCTRLR */

#define CSL_EMIF_IOCTRLR_IOCTRL_MASK     (0x0000FFFFu)
#define CSL_EMIF_IOCTRLR_IOCTRL_SHIFT    (0x00000000u)
#define CSL_EMIF_IOCTRLR_IOCTRL_RESETVAL (0x00000000u)

#define CSL_EMIF_IOCTRLR_RESETVAL        (0x00000000u)

/* IOSTATR */

#define CSL_EMIF_IOSTATR_IOSTAT_MASK     (0x0000000Fu)
#define CSL_EMIF_IOSTATR_IOSTAT_SHIFT    (0x00000000u)
#define CSL_EMIF_IOSTATR_IOSTAT_RESETVAL (0x00000000u)

#define CSL_EMIF_IOSTATR_RESETVAL        (0x00000000u)

/* NANDFCR */

#define CSL_EMIF_NANDFCR_CS5ECC_MASK     (0x00000800u)
#define CSL_EMIF_NANDFCR_CS5ECC_SHIFT    (0x0000000Bu)
#define CSL_EMIF_NANDFCR_CS5ECC_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFCR_CS4ECC_MASK     (0x00000400u)
#define CSL_EMIF_NANDFCR_CS4ECC_SHIFT    (0x0000000Au)
#define CSL_EMIF_NANDFCR_CS4ECC_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFCR_CS3ECC_MASK     (0x00000200u)
#define CSL_EMIF_NANDFCR_CS3ECC_SHIFT    (0x00000009u)
#define CSL_EMIF_NANDFCR_CS3ECC_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFCR_CS2ECC_MASK     (0x00000100u)
#define CSL_EMIF_NANDFCR_CS2ECC_SHIFT    (0x00000008u)
#define CSL_EMIF_NANDFCR_CS2ECC_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFCR_CS5NAND_MASK    (0x00000008u)
#define CSL_EMIF_NANDFCR_CS5NAND_SHIFT   (0x00000003u)
#define CSL_EMIF_NANDFCR_CS5NAND_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFCR_CS4NAND_MASK    (0x00000004u)
#define CSL_EMIF_NANDFCR_CS4NAND_SHIFT   (0x00000002u)
#define CSL_EMIF_NANDFCR_CS4NAND_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFCR_CS3NAND_MASK    (0x00000002u)
#define CSL_EMIF_NANDFCR_CS3NAND_SHIFT   (0x00000001u)
#define CSL_EMIF_NANDFCR_CS3NAND_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFCR_CS2NAND_MASK    (0x00000001u)
#define CSL_EMIF_NANDFCR_CS2NAND_SHIFT   (0x00000000u)
#define CSL_EMIF_NANDFCR_CS2NAND_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFCR_RESETVAL        (0x00000000u)

/* NANDFSR */

#define CSL_EMIF_NANDFSR_WAITST_MASK     (0x0000000Fu)
#define CSL_EMIF_NANDFSR_WAITST_SHIFT    (0x00000000u)
#define CSL_EMIF_NANDFSR_WAITST_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDFSR_RESETVAL        (0x00000000u)

/* NANDF1ECC */

#define CSL_EMIF_NANDF1ECC_P2048O_MASK   (0x08000000u)
#define CSL_EMIF_NANDF1ECC_P2048O_SHIFT  (0x0000001Bu)
#define CSL_EMIF_NANDF1ECC_P2048O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P1024O_MASK   (0x04000000u)
#define CSL_EMIF_NANDF1ECC_P1024O_SHIFT  (0x0000001Au)
#define CSL_EMIF_NANDF1ECC_P1024O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P512O_MASK    (0x02000000u)
#define CSL_EMIF_NANDF1ECC_P512O_SHIFT   (0x00000019u)
#define CSL_EMIF_NANDF1ECC_P512O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P256O_MASK    (0x01000000u)
#define CSL_EMIF_NANDF1ECC_P256O_SHIFT   (0x00000018u)
#define CSL_EMIF_NANDF1ECC_P256O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P128O_MASK    (0x00800000u)
#define CSL_EMIF_NANDF1ECC_P128O_SHIFT   (0x00000017u)
#define CSL_EMIF_NANDF1ECC_P128O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P64O_MASK     (0x00400000u)
#define CSL_EMIF_NANDF1ECC_P64O_SHIFT    (0x00000016u)
#define CSL_EMIF_NANDF1ECC_P64O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P32O_MASK     (0x00200000u)
#define CSL_EMIF_NANDF1ECC_P32O_SHIFT    (0x00000015u)
#define CSL_EMIF_NANDF1ECC_P32O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P16O_MASK     (0x00100000u)
#define CSL_EMIF_NANDF1ECC_P16O_SHIFT    (0x00000014u)
#define CSL_EMIF_NANDF1ECC_P16O_RESETVAL (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P8O_MASK      (0x00080000u)
#define CSL_EMIF_NANDF1ECC_P8O_SHIFT     (0x00000013u)
#define CSL_EMIF_NANDF1ECC_P8O_RESETVAL  (0x00000000u)

#define CSL_EMIF_NANDF1ECC_P4O_MASK      (0x00040000u)
#define CSL_EMIF_NANDF1ECC_P4O_SHIFT     (0x00000012u)
#define CSL_EMIF_NANDF1ECC_P4O_RESETVAL  (0x00000000u)