csl_mmcsd.h

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */ 

/** ============================================================================
 * @mainpage MMCSD CSL 3.x
 *   Path: \\(CSLPATH)\\ipmodules\\mmcsd\\src
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for
 * the MMCSD module across various devices. The CSL developer is expected to
 * refer to this document while designing APIs for these modules. Some of the
 * listed APIs may not be applicable to a given MMCSD module. While other cases
 * this list of APIs may not be sufficient to cover all the features of a
 * particular MMCSD Module. The CSL developer should use his discretion designing
 * new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02
 *  ============================================================================
 */

/** \file csl_mmcsd.h
    \brief MMC/SD functional layer API header file
    \internal
    \date   12 May, 2004
    \author Pratheesh Gangadhar ([e-mail])
 */

/* =============================================================================
 *  Revision History
 *  ===============
 *  12-Oct-2004 Hs Updated according to review comments
 *  01-sep-2004 Hs updated CSL_MmcsdObj and added CSL_MmcsdBaseAddress,
 *                 CSL_mmcsdParam, CSL_mmcsdContext,  CSL_mmcsdConfig structures.
 *                 - Updated comments for H/W control cmd and status query enums.
 *                 - Added prototypes for CSL_mmcsdGetBaseAdddress and
 *                   CSL_MmcsdHwSetupRaw.
 *                 - Changed prototypes of CSL_mmcsdInit, CSL_mmcsdOpen.
 *                 - Updated respective comments along with that of
 *                   CSL_mmcsdClose.
 *
 * =============================================================================
 */

#ifndef _CSL_MMCSD_H_
#define _CSL_MMCSD_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>
#include <csl_error.h>
//#include <csl_sysData.h>
#include <soc.h>
#include <csl_types.h>
#include <cslr_mmcsd.h>

/**
\defgroup CSL_MMCSD_API MMC/SD
   \internal Based on <b>Imaging and Audio Group MMCSD Detailed Design
             Specification Rev 1.00.w.05 </b>
*/
/**
\defgroup CSL_MMCSD_DATASTRUCT Data Structures
\ingroup CSL_MMCSD_API
*/
/**
\defgroup CSL_MMCSD_DEFINE  Defines
\ingroup CSL_MMCSD_API
*/
/**
\defgroup CSL_MMCSD_ENUM  Enumerated Data Types
\ingroup CSL_MMCSD_API
*/

/**
\defgroup CSL_MMCSD_FUNCTION  Functions
\ingroup CSL_MMCSD_API
*/

/*****************************************************************************\
        MMCSD global macro declarations
\*****************************************************************************/
/** \defgroup CSL_MMCSD_INTEN_DEFINE Interrupt Enable Masks
*   \ingroup CSL_MMCSD_DEFINE
*
*
* @{ */
#define CSL_MMCSD_INTEN_TRNDNE      CSL_FMKT (MMCSD_MMCIM_ETRNDNE, PERMIT)
                                /**< Enable Data transfer done interrupt */
#define CSL_MMCSD_INTEN_DATED       CSL_FMKT (MMCSD_MMCIM_EDATED, PERMIT)
                                /**< Enable DAT3 edge detect interrupt */
#define CSL_MMCSD_INTEN_DRRDY       CSL_FMKT (MMCSD_MMCIM_EDRRDY, PERMIT)
                                /**< Enable data receive ready interrupt */
#define CSL_MMCSD_INTEN_DXRDY       CSL_FMKT (MMCSD_MMCIM_EDXRDY, PERMIT)
                                /**< Enable data transmit ready interrupt */
#define CSL_MMCSD_INTEN_CRCRS       CSL_FMKT (MMCSD_MMCIM_ECRCRS, PERMIT)
                                /**< Enable response CRC error interrupt */
#define CSL_MMCSD_INTEN_CRCRD       CSL_FMKT (MMCSD_MMCIM_ECRCRD, PERMIT)
                                /**< Enable read-data CRC error interrupt */
#define CSL_MMCSD_INTEN_CRCWR       CSL_FMKT (MMCSD_MMCIM_ECRCWR, PERMIT)
                                /**< Enable write-data CRC error interrupt */
#define CSL_MMCSD_INTEN_TOUTRS      CSL_FMKT (MMCSD_MMCIM_ETOUTRS, PERMIT)
                                /**< Enable response time-out interrupt */
#define CSL_MMCSD_INTEN_TOUTRD      CSL_FMKT (MMCSD_MMCIM_ETOUTRD, PERMIT)
                                /**< Enable read-data time-out interrupt */
#define CSL_MMCSD_INTEN_RSPDNE      CSL_FMKT (MMCSD_MMCIM_ERSPDNE, PERMIT)
                                /**< Enable response/command done interrupt */
#define CSL_MMCSD_INTEN_BSYDNE      CSL_FMKT (MMCSD_MMCIM_EBSYDNE, PERMIT)
                                /**< Enable busy done interrupt */
#define CSL_MMCSD_INTEN_DATDNE      CSL_FMKT (MMCSD_MMCIM_EDATDNE, PERMIT)
                                /**< Enable data transfer done interrupt */
/**
@} */


/** \defgroup CSL_MMCSD_SDIOINT_DEFINE SDIO Interrupt Enable/Status Masks
*   \ingroup CSL_MMCSD_DEFINE
*
*
* @{ */

#define CSL_MMCSD_SDIOINT_RDWT      CSL_FMKT (MMCSD_SDIOIEN_RWSEN, ENABLE)
                                   /**< Enable read Wait interrupt */
#define CSL_MMCSD_SDIOINT_IOINT     CSL_FMKT (MMCSD_SDIOIEN_IOINTEN, ENABLE)
                                   /**< Enable SDIO card interrupt */

/**
@} */


/** \defgroup CSL_MMCSD_SDIOSTAT_DEFINE SDIO Status Masks
*   \ingroup CSL_MMCSD_DEFINE
*
*
* @{ */

#define CSL_MMCSD_SDIOSTAT_RDWT     CSL_FMKT (MMCSD_SDIOIEN_RDWTST, ENABLE)
                                   /**< Read wait operation in progress */
#define CSL_MMCSD_SDIOSTAT_INTPRD   CSL_FMKT (MMCSD_SDIOIEN_INTPRD, ENABLE)
                                   /**< Interrupt asserted */
#define CSL_MMCSD_SDIOSTAT_DAT1     CSL_FMKT (MMCSD_SDIOIEN_DAT1, ENABLE)
                                   /**< DAT1 status */

/**
@} */




/** \defgroup CSL_MMCSD_STAT_DEFINE MMC/SD Status Masks
*   \ingroup CSL_MMCSD_DEFINE
*
*
* @{ */

#define CSL_MMCSD_STAT0_TRNDNE      CSL_FMK (MMCSD_MMCST0_TRNDNE, 1)
                                /**< Data transfer of specified length done */
#define CSL_MMCSD_STAT0_DATED       CSL_FMK (MMCSD_MMCST0_DATED, 1)
                                /**< DAT3 edge detect */
#define CSL_MMCSD_STAT0_DRRDY       CSL_FMK (MMCSD_MMCST0_DRRDY, 1)
                                /**< Data receive ready detect */
#define CSL_MMCSD_STAT0_DXRDY       CSL_FMK (MMCSD_MMCST0_DXRDY, 1)
                                /**< Data transmit ready detect */
#define CSL_MMCSD_STAT0_CRCRS       CSL_FMK (MMCSD_MMCST0_CRCRS, 1)
                                /**< Response CRC error detect */
#define CSL_MMCSD_STAT0_CRCRD       CSL_FMK (MMCSD_MMCST0_CRCRD, 1)
                                /**< Read-data CRC error detect */
#define CSL_MMCSD_STAT0_CRCWR       CSL_FMK (MMCSD_MMCST0_CRCWR, 1)
                                /**< Write-data CRC error detect */
#define CSL_MMCSD_STAT0_TOUTRS      CSL_FMK (MMCSD_MMCST0_TOUTRS, 1)
                                /**< Response time-out detect */
#define CSL_MMCSD_STAT0_TOUTRD      CSL_FMK (MMCSD_MMCST0_TOUTRD, 1)
                                /**< Read-data time-out detect */
#define CSL_MMCSD_STAT0_RSPDNE      CSL_FMK (MMCSD_MMCST0_RSPDNE, 1)
                                /**< Write-data CRC error detect */
#define CSL_MMCSD_STAT0_BSYDNE      CSL_FMK (MMCSD_MMCST0_BSYDNE, 1)
                                /**< Response time-out detect */
#define CSL_MMCSD_STAT0_DATDNE      CSL_FMK (MMCSD_MMCST0_DATDNE, 1)
                                /**< Read-data time-out detect */

#define CSL_MMCSD_STAT1_BUSY        CSL_FMK (MMCSD_MMCST1_BUSY, 1)
                                /**< Busy signal detect */
#define CSL_MMCSD_STAT1_CLKLOW      CSL_FMK (MMCSD_MMCST1_CLKSTP, 1)
                                /**< CLK is held low. Possible reasons:
                                 Manual stop (CLKEN = 0), data receive full
                                 condition, or data transmit empty condition */
#define CSL_MMCSD_STAT1_DXEMP       CSL_FMK (MMCSD_MMCST1_DXEMP, 1)
                                /**< Data transmit empty */
#define CSL_MMCSD_STAT1_DRFUL       CSL_FMK (MMCSD_MMCST1_DRFUL, 1)
                                /**< Data receive full */
#define CSL_MMCSD_STAT1_DAT3ST      CSL_FMK (MMCSD_MMCST1_DAT3ST, 1)
                                /**< DAT3 status */
#define CSL_MMCSD_STAT1_FIFOEMP     CSL_FMK (MMCSD_MMCST1_FIFOEMP, 1)
                                /**< FIFO empty */
#define CSL_MMCSD_STAT1_FIFOFUL     CSL_FMK (MMCSD_MMCST1_FIFOFUL, 1)
                                /**< FIFO full */
/**
@} */


/** \defgroup CSL_MMCSD_RESET_DEFINE Reset Logic Select
*   \ingroup CSL_MMCSD_DEFINE
*
*
* @{ */
#define CSL_MMCSD_RESET_CMD      CSL_FMKT(MMCSD_MMCCTL_CMDRST, DISABLE)
                               /**< The CMD line portion is disabled and in
                                    reset state */
#define CSL_MMCSD_RESET_DAT      CSL_FMKT(MMCSD_MMCCTL_DATRST, DISABLE)
                               /**< The DAT line portion is disabled and in
                                    reset state */

/**
@} */



/** \defgroup CSL_MMCSD_CMD_FLAG_DEFINE Command Enhancements
*   \ingroup CSL_MMCSD_DEFINE
*
*
* @{ */

#define CSL_MMCSD_DCLR           CSL_FMKT(MMCSD_MMCCMD_DCLR, CLEAR)
                    /**< OR with CSL_MmcsdCmdType, when command has to be sent
                     with data receive/transmit clear */
#define CSL_MMCSD_GENDMAREQ      CSL_FMKT(MMCSD_MMCCMD_DMATRIG, YES)
                    /**< OR with CSL_MmcsdCmdType, when DMA transfer event has
                     to be generated */

/**
@} */


/*****************************************************************************\
        MMCSD global typedef declarations
\*****************************************************************************/

/**\defgroup CSL_MMCSD_MCLK_ENUM Memory Clock Control
*  \ingroup CSL_MMCSD_ENUM
*
*
@{*/
/** \brief MMC/SD memory clock control
*
*/