📄 dianyabiao.sim.rpt
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; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[2]~1 ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[2]~1 ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~4 ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~5 ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~5 ; out0 ;
+------------------------------------------------------------+------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+------------------------------------------------------------+------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------------------------------------------------+------------------------------------------------------------+------------------+
; |dianyabiao|sent~256 ; |dianyabiao|sent~256 ; out ;
; |dianyabiao|sent~257 ; |dianyabiao|sent~257 ; out ;
; |dianyabiao|sent~258 ; |dianyabiao|sent~258 ; out ;
; |dianyabiao|sent~259 ; |dianyabiao|sent~259 ; out ;
; |dianyabiao|sent~260 ; |dianyabiao|sent~260 ; out ;
; |dianyabiao|sent~261 ; |dianyabiao|sent~261 ; out ;
; |dianyabiao|sent~262 ; |dianyabiao|sent~262 ; out ;
; |dianyabiao|sent~263 ; |dianyabiao|sent~263 ; out ;
; |dianyabiao|sent~264 ; |dianyabiao|sent~264 ; out ;
; |dianyabiao|sent~265 ; |dianyabiao|sent~265 ; out ;
; |dianyabiao|sent~266 ; |dianyabiao|sent~266 ; out ;
; |dianyabiao|sent~267 ; |dianyabiao|sent~267 ; out ;
; |dianyabiao|sent~268 ; |dianyabiao|sent~268 ; out ;
; |dianyabiao|sent~269 ; |dianyabiao|sent~269 ; out ;
; |dianyabiao|sent~270 ; |dianyabiao|sent~270 ; out ;
; |dianyabiao|sent~271 ; |dianyabiao|sent~271 ; out ;
; |dianyabiao|sent~272 ; |dianyabiao|sent~272 ; out ;
; |dianyabiao|sent~273 ; |dianyabiao|sent~273 ; out ;
; |dianyabiao|sent~274 ; |dianyabiao|sent~274 ; out ;
; |dianyabiao|sent~275 ; |dianyabiao|sent~275 ; out ;
; |dianyabiao|sent~276 ; |dianyabiao|sent~276 ; out ;
; |dianyabiao|sent~277 ; |dianyabiao|sent~277 ; out ;
; |dianyabiao|sent~278 ; |dianyabiao|sent~278 ; out ;
; |dianyabiao|sent~279 ; |dianyabiao|sent~279 ; out ;
; |dianyabiao|sent~280 ; |dianyabiao|sent~280 ; out ;
; |dianyabiao|sent~281 ; |dianyabiao|sent~281 ; out ;
; |dianyabiao|sent~282 ; |dianyabiao|sent~282 ; out ;
; |dianyabiao|sent~283 ; |dianyabiao|sent~283 ; out ;
; |dianyabiao|sent~284 ; |dianyabiao|sent~284 ; out ;
; |dianyabiao|sent~285 ; |dianyabiao|sent~285 ; out ;
; |dianyabiao|sent~286 ; |dianyabiao|sent~286 ; out ;
; |dianyabiao|sent~287 ; |dianyabiao|sent~287 ; out ;
; |dianyabiao|sent[0]~reg0 ; |dianyabiao|sent[0]~reg0 ; regout ;
; |dianyabiao|sent[1]~reg0 ; |dianyabiao|sent[1]~reg0 ; regout ;
; |dianyabiao|sent[2]~reg0 ; |dianyabiao|sent[2]~reg0 ; regout ;
; |dianyabiao|sent[3]~reg0 ; |dianyabiao|sent[3]~reg0 ; regout ;
; |dianyabiao|sent[4]~reg0 ; |dianyabiao|sent[4]~reg0 ; regout ;
; |dianyabiao|sent[5]~reg0 ; |dianyabiao|sent[5]~reg0 ; regout ;
; |dianyabiao|sent[6]~reg0 ; |dianyabiao|sent[6]~reg0 ; regout ;
; |dianyabiao|sent[7]~reg0 ; |dianyabiao|sent[7]~reg0 ; regout ;
; |dianyabiao|start ; |dianyabiao|start ; pin_out ;
; |dianyabiao|ale ; |dianyabiao|ale ; pin_out ;
; |dianyabiao|en ; |dianyabiao|en ; pin_out ;
; |dianyabiao|abc_in[0] ; |dianyabiao|abc_in[0] ; out ;
; |dianyabiao|abc_in[1] ; |dianyabiao|abc_in[1] ; out ;
; |dianyabiao|abc_in[2] ; |dianyabiao|abc_in[2] ; out ;
; |dianyabiao|abc_out[0] ; |dianyabiao|abc_out[0] ; pin_out ;
; |dianyabiao|abc_out[1] ; |dianyabiao|abc_out[1] ; pin_out ;
; |dianyabiao|abc_out[2] ; |dianyabiao|abc_out[2] ; pin_out ;
; |dianyabiao|sent[0] ; |dianyabiao|sent[0] ; pin_out ;
; |dianyabiao|sent[1] ; |dianyabiao|sent[1] ; pin_out ;
; |dianyabiao|sent[2] ; |dianyabiao|sent[2] ; pin_out ;
; |dianyabiao|sent[3] ; |dianyabiao|sent[3] ; pin_out ;
; |dianyabiao|sent[4] ; |dianyabiao|sent[4] ; pin_out ;
; |dianyabiao|sent[5] ; |dianyabiao|sent[5] ; pin_out ;
; |dianyabiao|sent[6] ; |dianyabiao|sent[6] ; pin_out ;
; |dianyabiao|sent[7] ; |dianyabiao|sent[7] ; pin_out ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~1 ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~1 ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~2 ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~2 ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[2]~1 ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[2]~1 ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~4 ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~5 ; |dianyabiao|lpm_add_sub:Add0|addcore:adder|_~5 ; out0 ;
+------------------------------------------------------------+------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sun May 17 11:26:19 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off dianyabiao -c dianyabiao
Info: Using vector source file "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vwf"
Warning: Ignored node in vector source file. Can't find corresponding node name "regl[7]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "regl[6]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "regl[5]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "regl[4]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "regl[3]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "regl[2]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "regl[1]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "regl[0]" in design.
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 51.47 %
Info: Number of transitions in simulation is 6534
Info: Quartus II Simulator was successful. 0 errors, 8 warnings
Info: Allocated 102 megabytes of memory during processing
Info: Processing ended: Sun May 17 11:26:22 2009
Info: Elapsed time: 00:00:03
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