dianyabiao.tan.rpt

对adc0809的控制及数码管输出

+-------------------------------------------------------------------------+
; tsu                                                                     ;
+-------+--------------+------------+------+-------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To                ; To Clock ;
+-------+--------------+------------+------+-------------------+----------+
; N/A   ; None         ; -0.400 ns  ; eoc  ; current_state.st4 ; clk      ;
; N/A   ; None         ; -0.400 ns  ; eoc  ; current_state.st3 ; clk      ;
; N/A   ; None         ; -0.500 ns  ; eoc  ; current_state.st5 ; clk      ;
+-------+--------------+------------+------+-------------------+----------+


+------------------------------------------------------------------------------+
; tco                                                                          ;
+-------+--------------+------------+-------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To      ; From Clock ;
+-------+--------------+------------+-------------------+---------+------------+
; N/A   ; None         ; 18.500 ns  ; current_state.st5 ; en      ; clk        ;
; N/A   ; None         ; 18.400 ns  ; current_state.st6 ; en      ; clk        ;
; N/A   ; None         ; 14.900 ns  ; current_state.st1 ; ale     ; clk        ;
; N/A   ; None         ; 14.900 ns  ; current_state.st2 ; start   ; clk        ;
; N/A   ; None         ; 14.400 ns  ; jiao[1]~reg0      ; jiao[1] ; clk        ;
; N/A   ; None         ; 14.400 ns  ; jiao[0]~reg0      ; jiao[0] ; clk        ;
; N/A   ; None         ; 14.300 ns  ; jiao[3]~reg0      ; jiao[3] ; clk        ;
; N/A   ; None         ; 14.300 ns  ; jiao[2]~reg0      ; jiao[2] ; clk        ;
+-------+--------------+------------+-------------------+---------+------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+-----------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To         ;
+-------+-------------------+-----------------+-----------+------------+
; N/A   ; None              ; 13.700 ns       ; abc_in[2] ; abc_out[2] ;
; N/A   ; None              ; 13.500 ns       ; abc_in[0] ; abc_out[0] ;
; N/A   ; None              ; 13.400 ns       ; abc_in[1] ; abc_out[1] ;
+-------+-------------------+-----------------+-----------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; 2.000 ns  ; eoc  ; current_state.st5 ; clk      ;
; N/A           ; None        ; 1.900 ns  ; eoc  ; current_state.st4 ; clk      ;
; N/A           ; None        ; 1.900 ns  ; eoc  ; current_state.st3 ; clk      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun May 24 08:53:56 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dianyabiao -c dianyabiao
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 166.67 MHz between source register "jiao[0]~reg0" and destination register "jiao[0]~reg0"
    Info: fmax restricted to Clock High delay (3.0 ns) plus Clock Low delay (3.0 ns) : restricted to 6.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_J36; Fanout = 2; REG Node = 'jiao[0]~reg0'
            Info: 2: + IC(0.200 ns) + CELL(1.100 ns) = 1.300 ns; Loc. = LC2_J36; Fanout = 2; REG Node = 'jiao[0]~reg0'
            Info: Total cell delay = 1.100 ns ( 84.62 % )
            Info: Total interconnect delay = 0.200 ns ( 15.38 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 7.900 ns
                Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(4.900 ns) + CELL(0.000 ns) = 7.900 ns; Loc. = LC2_J36; Fanout = 2; REG Node = 'jiao[0]~reg0'
                Info: Total cell delay = 3.000 ns ( 37.97 % )
                Info: Total interconnect delay = 4.900 ns ( 62.03 % )
            Info: - Longest clock path from clock "clk" to source register is 7.900 ns
                Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(4.900 ns) + CELL(0.000 ns) = 7.900 ns; Loc. = LC2_J36; Fanout = 2; REG Node = 'jiao[0]~reg0'
                Info: Total cell delay = 3.000 ns ( 37.97 % )
                Info: Total interconnect delay = 4.900 ns ( 62.03 % )
        Info: + Micro clock to output delay of source is 0.700 ns
        Info: + Micro setup delay of destination is 0.700 ns
Info: tsu for register "current_state.st4" (data pin = "eoc", clock pin = "clk") is -0.400 ns
    Info: + Longest pin to register delay is 7.100 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_30; Fanout = 3; PIN Node = 'eoc'
        Info: 2: + IC(3.100 ns) + CELL(1.000 ns) = 7.100 ns; Loc. = LC6_G20; Fanout = 2; REG Node = 'current_state.st4'
        Info: Total cell delay = 4.000 ns ( 56.34 % )
        Info: Total interconnect delay = 3.100 ns ( 43.66 % )
    Info: + Micro setup delay of destination is 0.700 ns
    Info: - Shortest clock path from clock "clk" to destination register is 8.200 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(5.200 ns) + CELL(0.000 ns) = 8.200 ns; Loc. = LC6_G20; Fanout = 2; REG Node = 'current_state.st4'
        Info: Total cell delay = 3.000 ns ( 36.59 % )
        Info: Total interconnect delay = 5.200 ns ( 63.41 % )
Info: tco from clock "clk" to destination pin "en" through register "current_state.st5" is 18.500 ns
    Info: + Longest clock path from clock "clk" to source register is 8.200 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(5.200 ns) + CELL(0.000 ns) = 8.200 ns; Loc. = LC2_G20; Fanout = 2; REG Node = 'current_state.st5'
        Info: Total cell delay = 3.000 ns ( 36.59 % )
        Info: Total interconnect delay = 5.200 ns ( 63.41 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Longest register to pin delay is 9.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_G20; Fanout = 2; REG Node = 'current_state.st5'
        Info: 2: + IC(1.600 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC5_G34; Fanout = 1; COMB Node = 'en~0'
        Info: 3: + IC(1.900 ns) + CELL(4.600 ns) = 9.600 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'en'
        Info: Total cell delay = 6.100 ns ( 63.54 % )
        Info: Total interconnect delay = 3.500 ns ( 36.46 % )
Info: Longest tpd from source pin "abc_in[2]" to destination pin "abc_out[2]" is 13.700 ns
    Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_8; Fanout = 1; PIN Node = 'abc_in[2]'
    Info: 2: + IC(2.800 ns) + CELL(1.400 ns) = 7.200 ns; Loc. = LC5_A28; Fanout = 1; COMB Node = 'abc_out[2]~2'
    Info: 3: + IC(1.900 ns) + CELL(4.600 ns) = 13.700 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'abc_out[2]'
    Info: Total cell delay = 9.000 ns ( 65.69 % )
    Info: Total interconnect delay = 4.700 ns ( 34.31 % )
Info: th for register "current_state.st5" (data pin = "eoc", clock pin = "clk") is 2.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 8.200 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(5.200 ns) + CELL(0.000 ns) = 8.200 ns; Loc. = LC2_G20; Fanout = 2; REG Node = 'current_state.st5'
        Info: Total cell delay = 3.000 ns ( 36.59 % )
        Info: Total interconnect delay = 5.200 ns ( 63.41 % )
    Info: + Micro hold delay of destination is 0.800 ns
    Info: - Shortest pin to register delay is 7.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_30; Fanout = 3; PIN Node = 'eoc'
        Info: 2: + IC(3.100 ns) + CELL(0.900 ns) = 7.000 ns; Loc. = LC2_G20; Fanout = 2; REG Node = 'current_state.st5'
        Info: Total cell delay = 3.900 ns ( 55.71 % )
        Info: Total interconnect delay = 3.100 ns ( 44.29 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 119 megabytes of memory during processing
    Info: Processing ended: Sun May 24 08:53:57 2009
    Info: Elapsed time: 00:00:01