prev_cmp_dianyabiao.qmsg

对adc0809的控制及数码管输出

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sent\[6\]~reg0 data_in VCC " "Warning (14130): Reduced register \"sent\[6\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "sent\[7\]~reg0 High " "Info: Power-up level of register \"sent\[7\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sent\[7\]~reg0 data_in VCC " "Warning (14130): Reduced register \"sent\[7\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|dianyabiao\|current_state 7 " "Info: State machine \"\|dianyabiao\|current_state\" contains 7 states" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|dianyabiao\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|dianyabiao\|current_state\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|dianyabiao\|current_state " "Info: Encoding result for state machine \"\|dianyabiao\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "7 " "Info: Completed encoding using 7 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st6 " "Info: Encoded state bit \"current_state.st6\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st5 " "Info: Encoded state bit \"current_state.st5\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st4 " "Info: Encoded state bit \"current_state.st4\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st3 " "Info: Encoded state bit \"current_state.st3\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st2 " "Info: Encoded state bit \"current_state.st2\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st1 " "Info: Encoded state bit \"current_state.st1\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st0 " "Info: Encoded state bit \"current_state.st0\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dianyabiao\|current_state.st0 0000000 " "Info: State \"\|dianyabiao\|current_state.st0\" uses code string \"0000000\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dianyabiao\|current_state.st1 0000011 " "Info: State \"\|dianyabiao\|current_state.st1\" uses code string \"0000011\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dianyabiao\|current_state.st2 0000101 " "Info: State \"\|dianyabiao\|current_state.st2\" uses code string \"0000101\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dianyabiao\|current_state.st3 0001001 " "Info: State \"\|dianyabiao\|current_state.st3\" uses code string \"0001001\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dianyabiao\|current_state.st4 0010001 " "Info: State \"\|dianyabiao\|current_state.st4\" uses code string \"0010001\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dianyabiao\|current_state.st5 0100001 " "Info: State \"\|dianyabiao\|current_state.st5\" uses code string \"0100001\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dianyabiao\|current_state.st6 1000001 " "Info: State \"\|dianyabiao\|current_state.st6\" uses code string \"1000001\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "sent\[0\] GND " "Warning (13410): Pin \"sent\[0\]\" stuck at GND" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sent\[1\] VCC " "Warning (13410): Pin \"sent\[1\]\" stuck at VCC" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sent\[2\] GND " "Warning (13410): Pin \"sent\[2\]\" stuck at GND" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sent\[3\] GND " "Warning (13410): Pin \"sent\[3\]\" stuck at GND" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sent\[4\] VCC " "Warning (13410): Pin \"sent\[4\]\" stuck at VCC" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sent\[5\] VCC " "Warning (13410): Pin \"sent\[5\]\" stuck at VCC" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sent\[6\] VCC " "Warning (13410): Pin \"sent\[6\]\" stuck at VCC" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sent\[7\] VCC " "Warning (13410): Pin \"sent\[7\]\" stuck at VCC" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Warning: Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d\[0\] " "Warning (15610): No output dependent on input pin \"d\[0\]\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d\[1\] " "Warning (15610): No output dependent on input pin \"d\[1\]\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d\[2\] " "Warning (15610): No output dependent on input pin \"d\[2\]\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d\[3\] " "Warning (15610): No output dependent on input pin \"d\[3\]\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d\[4\] " "Warning (15610): No output dependent on input pin \"d\[4\]\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d\[5\] " "Warning (15610): No output dependent on input pin \"d\[5\]\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d\[6\] " "Warning (15610): No output dependent on input pin \"d\[6\]\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "d\[7\] " "Warning (15610): No output dependent on input pin \"d\[7\]\"" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "46 " "Info: Implemented 46 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "15 " "Info: Implemented 15 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 53 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 53 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "166 " "Info: Allocated 166 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 24 08:47:19 2009 " "Info: Processing ended: Sun May 24 08:47:19 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 24 08:47:21 2009 " "Info: Processing started: Sun May 24 08:47:21 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off dianyabiao -c dianyabiao " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dianyabiao -c dianyabiao" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "dianyabiao EP1K50QC208-3 " "Info: Selected device EP1K50QC208-3 for design \"dianyabiao\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0}
{ "Info" "IF10KE_F10KE_WIRE_LUT_INSERTED" "3 " "Info: Inserted 3 logic cells in first fitting attempt" {  } {  } 0 0 "Inserted %1!d! logic cells in first fitting attempt" 0 0 "" 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Sun May 24 2009 08:47:22 " "Info: Started fitting attempt 1 on Sun May 24 2009 at 08:47:22" {  } {  } 0 0 "Started fitting attempt %1!d! on %2!s! at %3!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}