dianyabiao.map.qmsg

对adc0809的控制及数码管输出

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 24 08:53:42 2009 " "Info: Processing started: Sun May 24 08:53:42 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dianyabiao -c dianyabiao " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianyabiao -c dianyabiao" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dianyabiao.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dianyabiao.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dianyabiao-bhv " "Info: Found design unit 1: dianyabiao-bhv" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 dianyabiao " "Info: Found entity 1: dianyabiao" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_rom2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file data_rom2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_rom2-SYN " "Info: Found design unit 1: data_rom2-SYN" {  } { { "data_rom2.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/data_rom2.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 data_rom2 " "Info: Found entity 1: data_rom2" {  } { { "data_rom2.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/data_rom2.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dianyabiao " "Info: Elaborating entity \"dianyabiao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sp_1a dianyabiao.vhd(73) " "Warning (10036): Verilog HDL or VHDL warning at dianyabiao.vhd(73): object \"sp_1a\" assigned a value but never read" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 73 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sp_2a dianyabiao.vhd(73) " "Warning (10036): Verilog HDL or VHDL warning at dianyabiao.vhd(73): object \"sp_2a\" assigned a value but never read" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 73 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sp_3a dianyabiao.vhd(73) " "Warning (10036): Verilog HDL or VHDL warning at dianyabiao.vhd(73): object \"sp_3a\" assigned a value but never read" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 73 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sp_4a dianyabiao.vhd(73) " "Warning (10036): Verilog HDL or VHDL warning at dianyabiao.vhd(73): object \"sp_4a\" assigned a value but never read" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 73 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d dianyabiao.vhd(96) " "Warning (10492): VHDL Process Statement warning at dianyabiao.vhd(96): signal \"d\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 96 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "regl dianyabiao.vhd(80) " "Warning (10631): VHDL Process Statement warning at dianyabiao.vhd(80): inferring latch(es) for signal or variable \"regl\", which holds its previous value in one or more paths through the process" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 80 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "regl\[0\] dianyabiao.vhd(80) " "Info (10041): Inferred latch for \"regl\[0\]\" at dianyabiao.vhd(80)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "regl\[1\] dianyabiao.vhd(80) " "Info (10041): Inferred latch for \"regl\[1\]\" at dianyabiao.vhd(80)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "regl\[2\] dianyabiao.vhd(80) " "Info (10041): Inferred latch for \"regl\[2\]\" at dianyabiao.vhd(80)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "regl\[3\] dianyabiao.vhd(80) " "Info (10041): Inferred latch for \"regl\[3\]\" at dianyabiao.vhd(80)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "regl\[4\] dianyabiao.vhd(80) " "Info (10041): Inferred latch for \"regl\[4\]\" at dianyabiao.vhd(80)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "regl\[5\] dianyabiao.vhd(80) " "Info (10041): Inferred latch for \"regl\[5\]\" at dianyabiao.vhd(80)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}