dianyabiao.fnsim.qmsg

对adc0809的控制及数码管输出

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 17 11:26:08 2009 " "Info: Processing started: Sun May 17 11:26:08 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dianyabiao -c dianyabiao --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianyabiao -c dianyabiao --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dianyabiao.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dianyabiao.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dianyabiao-bhv " "Info: Found design unit 1: dianyabiao-bhv" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 dianyabiao " "Info: Found entity 1: dianyabiao" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/d电路/EDA/d电压表/vhdl程序/data_rom2.vhd " "Warning: Can't analyze file -- file G:/d电路/EDA/d电压表/vhdl程序/data_rom2.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dianyabiao " "Info: Elaborating entity \"dianyabiao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "current_state dianyabiao.vhd(32) " "Warning (10540): VHDL Signal Declaration warning at dianyabiao.vhd(32): used explicit default value for signal \"current_state\" because signal was never assigned a value" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 32 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "next_state dianyabiao.vhd(32) " "Warning (10036): Verilog HDL or VHDL warning at dianyabiao.vhd(32): object \"next_state\" assigned a value but never read" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 32 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "regl\[7\] dianyabiao.vhd(33) " "Warning (10873): Using initial value X (don't care) for net \"regl\[7\]\" at dianyabiao.vhd(33)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 33 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "regl\[6\] dianyabiao.vhd(33) " "Warning (10873): Using initial value X (don't care) for net \"regl\[6\]\" at dianyabiao.vhd(33)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 33 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "regl\[5\] dianyabiao.vhd(33) " "Warning (10873): Using initial value X (don't care) for net \"regl\[5\]\" at dianyabiao.vhd(33)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 33 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "regl\[4\] dianyabiao.vhd(33) " "Warning (10873): Using initial value X (don't care) for net \"regl\[4\]\" at dianyabiao.vhd(33)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 33 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "regl\[3\] dianyabiao.vhd(33) " "Warning (10873): Using initial value X (don't care) for net \"regl\[3\]\" at dianyabiao.vhd(33)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 33 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "regl\[2\] dianyabiao.vhd(33) " "Warning (10873): Using initial value X (don't care) for net \"regl\[2\]\" at dianyabiao.vhd(33)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 33 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "regl\[1\] dianyabiao.vhd(33) " "Warning (10873): Using initial value X (don't care) for net \"regl\[1\]\" at dianyabiao.vhd(33)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 33 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "regl\[0\] dianyabiao.vhd(33) " "Warning (10873): Using initial value X (don't care) for net \"regl\[0\]\" at dianyabiao.vhd(33)" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 33 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" {  } { { "dianyabiao.vhd" "Add0" { Text "G:/d电路/EDA/d电压表/vhdl程序/dianyabiao.vhd" 77 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}