prev_cmp_dianyabiao.tan.qmsg

对adc0809的控制及数码管输出

{ "Info" "ITDB_TH_RESULT" "current_state.st5 eoc clk 2.000 ns register " "Info: th for register \"current_state.st5\" (data pin = \"eoc\", clock pin = \"clk\") is 2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_7 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.200 ns) + CELL(0.000 ns) 8.200 ns current_state.st5 2 REG LC2_G20 2 " "Info: 2: + IC(5.200 ns) + CELL(0.000 ns) = 8.200 ns; Loc. = LC2_G20; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { clk current_state.st5 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 36.59 % ) " "Info: Total cell delay = 3.000 ns ( 36.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns ( 63.41 % ) " "Info: Total interconnect delay = 5.200 ns ( 63.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk current_state.st5 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} current_state.st5 {} } { 0.000ns 0.000ns 5.200ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.800 ns + " "Info: + Micro hold delay of destination is 0.800 ns" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns eoc 1 PIN PIN_30 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_30; Fanout = 3; PIN Node = 'eoc'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoc } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.900 ns) 7.000 ns current_state.st5 2 REG LC2_G20 2 " "Info: 2: + IC(3.100 ns) + CELL(0.900 ns) = 7.000 ns; Loc. = LC2_G20; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { eoc current_state.st5 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 55.71 % ) " "Info: Total cell delay = 3.900 ns ( 55.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 44.29 % ) " "Info: Total interconnect delay = 3.100 ns ( 44.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { eoc current_state.st5 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { eoc {} eoc~out {} current_state.st5 {} } { 0.000ns 0.000ns 3.100ns } { 0.000ns 3.000ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk current_state.st5 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} current_state.st5 {} } { 0.000ns 0.000ns 5.200ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { eoc current_state.st5 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { eoc {} eoc~out {} current_state.st5 {} } { 0.000ns 0.000ns 3.100ns } { 0.000ns 3.000ns 0.900ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 24 08:47:31 2009 " "Info: Processing ended: Sun May 24 08:47:31 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}