prev_cmp_dianyabiao.tan.qmsg

对adc0809的控制及数码管输出

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 7 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register jiao\[0\]~reg0 jiao\[0\]~reg0 166.67 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 166.67 MHz between source register \"jiao\[0\]~reg0\" and destination register \"jiao\[0\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.0 ns 3.0 ns 6.0 ns " "Info: fmax restricted to Clock High delay (3.0 ns) plus Clock Low delay (3.0 ns) : restricted to 6.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.300 ns + Longest register register " "Info: + Longest register to register delay is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao\[0\]~reg0 1 REG LC2_J36 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_J36; Fanout = 2; REG Node = 'jiao\[0\]~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao[0]~reg0 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.100 ns) 1.300 ns jiao\[0\]~reg0 2 REG LC2_J36 2 " "Info: 2: + IC(0.200 ns) + CELL(1.100 ns) = 1.300 ns; Loc. = LC2_J36; Fanout = 2; REG Node = 'jiao\[0\]~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { jiao[0]~reg0 jiao[0]~reg0 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.100 ns ( 84.62 % ) " "Info: Total cell delay = 1.100 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 15.38 % ) " "Info: Total interconnect delay = 0.200 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { jiao[0]~reg0 jiao[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "1.300 ns" { jiao[0]~reg0 {} jiao[0]~reg0 {} } { 0.000ns 0.200ns } { 0.000ns 1.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_7 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(0.000 ns) 7.900 ns jiao\[0\]~reg0 2 REG LC2_J36 2 " "Info: 2: + IC(4.900 ns) + CELL(0.000 ns) = 7.900 ns; Loc. = LC2_J36; Fanout = 2; REG Node = 'jiao\[0\]~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { clk jiao[0]~reg0 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 37.97 % ) " "Info: Total cell delay = 3.000 ns ( 37.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 62.03 % ) " "Info: Total interconnect delay = 4.900 ns ( 62.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk jiao[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} jiao[0]~reg0 {} } { 0.000ns 0.000ns 4.900ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_7 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.900 ns) + CELL(0.000 ns) 7.900 ns jiao\[0\]~reg0 2 REG LC2_J36 2 " "Info: 2: + IC(4.900 ns) + CELL(0.000 ns) = 7.900 ns; Loc. = LC2_J36; Fanout = 2; REG Node = 'jiao\[0\]~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { clk jiao[0]~reg0 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 37.97 % ) " "Info: Total cell delay = 3.000 ns ( 37.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 62.03 % ) " "Info: Total interconnect delay = 4.900 ns ( 62.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk jiao[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} jiao[0]~reg0 {} } { 0.000ns 0.000ns 4.900ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk jiao[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} jiao[0]~reg0 {} } { 0.000ns 0.000ns 4.900ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk jiao[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} jiao[0]~reg0 {} } { 0.000ns 0.000ns 4.900ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { jiao[0]~reg0 jiao[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "1.300 ns" { jiao[0]~reg0 {} jiao[0]~reg0 {} } { 0.000ns 0.200ns } { 0.000ns 1.100ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk jiao[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} jiao[0]~reg0 {} } { 0.000ns 0.000ns 4.900ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.900 ns" { clk jiao[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.900 ns" { clk {} clk~out {} jiao[0]~reg0 {} } { 0.000ns 0.000ns 4.900ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { jiao[0]~reg0 {} } {  } {  } "" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 129 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.st4 eoc clk -0.400 ns register " "Info: tsu for register \"current_state.st4\" (data pin = \"eoc\", clock pin = \"clk\") is -0.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.100 ns + Longest pin register " "Info: + Longest pin to register delay is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns eoc 1 PIN PIN_30 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_30; Fanout = 3; PIN Node = 'eoc'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoc } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(1.000 ns) 7.100 ns current_state.st4 2 REG LC6_G20 2 " "Info: 2: + IC(3.100 ns) + CELL(1.000 ns) = 7.100 ns; Loc. = LC6_G20; Fanout = 2; REG Node = 'current_state.st4'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { eoc current_state.st4 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 56.34 % ) " "Info: Total cell delay = 4.000 ns ( 56.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 43.66 % ) " "Info: Total interconnect delay = 3.100 ns ( 43.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.100 ns" { eoc current_state.st4 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.100 ns" { eoc {} eoc~out {} current_state.st4 {} } { 0.000ns 0.000ns 3.100ns } { 0.000ns 3.000ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_7 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.200 ns) + CELL(0.000 ns) 8.200 ns current_state.st4 2 REG LC6_G20 2 " "Info: 2: + IC(5.200 ns) + CELL(0.000 ns) = 8.200 ns; Loc. = LC6_G20; Fanout = 2; REG Node = 'current_state.st4'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { clk current_state.st4 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 36.59 % ) " "Info: Total cell delay = 3.000 ns ( 36.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns ( 63.41 % ) " "Info: Total interconnect delay = 5.200 ns ( 63.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk current_state.st4 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} current_state.st4 {} } { 0.000ns 0.000ns 5.200ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.100 ns" { eoc current_state.st4 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.100 ns" { eoc {} eoc~out {} current_state.st4 {} } { 0.000ns 0.000ns 3.100ns } { 0.000ns 3.000ns 1.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk current_state.st4 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} current_state.st4 {} } { 0.000ns 0.000ns 5.200ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk en current_state.st5 18.500 ns register " "Info: tco from clock \"clk\" to destination pin \"en\" through register \"current_state.st5\" is 18.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_7 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_7; Fanout = 14; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.200 ns) + CELL(0.000 ns) 8.200 ns current_state.st5 2 REG LC2_G20 2 " "Info: 2: + IC(5.200 ns) + CELL(0.000 ns) = 8.200 ns; Loc. = LC2_G20; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { clk current_state.st5 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 36.59 % ) " "Info: Total cell delay = 3.000 ns ( 36.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.200 ns ( 63.41 % ) " "Info: Total interconnect delay = 5.200 ns ( 63.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk current_state.st5 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} current_state.st5 {} } { 0.000ns 0.000ns 5.200ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.600 ns + Longest register pin " "Info: + Longest register to pin delay is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st5 1 REG LC2_G20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_G20; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { current_state.st5 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.500 ns) 3.100 ns en~0 2 COMB LC5_G34 1 " "Info: 2: + IC(1.600 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC5_G34; Fanout = 1; COMB Node = 'en~0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { current_state.st5 en~0 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(4.600 ns) 9.600 ns en 3 PIN PIN_28 0 " "Info: 3: + IC(1.900 ns) + CELL(4.600 ns) = 9.600 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'en'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { en~0 en } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.100 ns ( 63.54 % ) " "Info: Total cell delay = 6.100 ns ( 63.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 36.46 % ) " "Info: Total interconnect delay = 3.500 ns ( 36.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.600 ns" { current_state.st5 en~0 en } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "9.600 ns" { current_state.st5 {} en~0 {} en {} } { 0.000ns 1.600ns 1.900ns } { 0.000ns 1.500ns 4.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { clk current_state.st5 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.200 ns" { clk {} clk~out {} current_state.st5 {} } { 0.000ns 0.000ns 5.200ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.600 ns" { current_state.st5 en~0 en } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "9.600 ns" { current_state.st5 {} en~0 {} en {} } { 0.000ns 1.600ns 1.900ns } { 0.000ns 1.500ns 4.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "abc_in\[2\] abc_out\[2\] 13.700 ns Longest " "Info: Longest tpd from source pin \"abc_in\[2\]\" to destination pin \"abc_out\[2\]\" is 13.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns abc_in\[2\] 1 PIN PIN_8 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_8; Fanout = 1; PIN Node = 'abc_in\[2\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { abc_in[2] } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.400 ns) 7.200 ns abc_out\[2\]~2 2 COMB LC5_A28 1 " "Info: 2: + IC(2.800 ns) + CELL(1.400 ns) = 7.200 ns; Loc. = LC5_A28; Fanout = 1; COMB Node = 'abc_out\[2\]~2'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.200 ns" { abc_in[2] abc_out[2]~2 } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(4.600 ns) 13.700 ns abc_out\[2\] 3 PIN PIN_11 0 " "Info: 3: + IC(1.900 ns) + CELL(4.600 ns) = 13.700 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'abc_out\[2\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { abc_out[2]~2 abc_out[2] } "NODE_NAME" } } { "dianyabiao.vhd" "" { Text "G:/d电路/EDA/周爱义/d电压表/vhdl程序/dianyabiao.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 65.69 % ) " "Info: Total cell delay = 9.000 ns ( 65.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns ( 34.31 % ) " "Info: Total interconnect delay = 4.700 ns ( 34.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.700 ns" { abc_in[2] abc_out[2]~2 abc_out[2] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "13.700 ns" { abc_in[2] {} abc_in[2]~out {} abc_out[2]~2 {} abc_out[2] {} } { 0.000ns 0.000ns 2.800ns 1.900ns } { 0.000ns 3.000ns 1.400ns 4.600ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}