dianyabiao.hier_info

对adc0809的控制及数码管输出

|dianyabiao
d[0] => regl[0].DATAIN
d[1] => regl[1].DATAIN
d[2] => regl[2].DATAIN
d[3] => regl[3].DATAIN
d[4] => regl[4].DATAIN
d[5] => regl[5].DATAIN
d[6] => regl[6].DATAIN
d[7] => regl[7].DATAIN
clk => data_rom1:data1.outclock
clk => data_rom1:data1.inclock
clk => data_rom2:data2.outclock
clk => data_rom2:data2.inclock
clk => data_rom3:data3.outclock
clk => data_rom3:data3.inclock
clk => data_rom4:data4.outclock
clk => \show:a[2].CLK
clk => \show:a[1].CLK
clk => \show:a[0].CLK
clk => sent[7]~reg0.CLK
clk => sent[6]~reg0.CLK
clk => sent[5]~reg0.CLK
clk => sent[4]~reg0.CLK
clk => sent[3]~reg0.CLK
clk => sent[2]~reg0.CLK
clk => sent[1]~reg0.CLK
clk => sent[0]~reg0.CLK
clk => jiao[3]~reg0.CLK
clk => jiao[2]~reg0.CLK
clk => jiao[1]~reg0.CLK
clk => jiao[0]~reg0.CLK
clk => data_rom4:data4.inclock
clk => current_state~0.IN1
eoc => next_state.st5.DATAB
eoc => Selector0.IN3
eoc => Selector1.IN0
start <= current_state.st2.DB_MAX_OUTPUT_PORT_TYPE
ale <= current_state.st1.DB_MAX_OUTPUT_PORT_TYPE
en <= en~0.DB_MAX_OUTPUT_PORT_TYPE
abc_in[0] => abc_out[0].DATAIN
abc_in[1] => abc_out[1].DATAIN
abc_in[2] => abc_out[2].DATAIN
abc_out[0] <= abc_in[0].DB_MAX_OUTPUT_PORT_TYPE
abc_out[1] <= abc_in[1].DB_MAX_OUTPUT_PORT_TYPE
abc_out[2] <= abc_in[2].DB_MAX_OUTPUT_PORT_TYPE
sent[0] <= sent[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sent[1] <= sent[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sent[2] <= sent[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sent[3] <= sent[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sent[4] <= sent[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sent[5] <= sent[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sent[6] <= sent[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sent[7] <= sent[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
jiao[0] <= jiao[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
jiao[1] <= jiao[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
jiao[2] <= jiao[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
jiao[3] <= jiao[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dianyabiao|data_rom4:data4
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
address[6] => lpm_rom:lpm_rom_component.address[6]
address[7] => lpm_rom:lpm_rom_component.address[7]
inclock => lpm_rom:lpm_rom_component.inclock
outclock => lpm_rom:lpm_rom_component.outclock
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]


|dianyabiao|data_rom4:data4|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
inclock => altrom:srom.clocki
outclock => altrom:srom.clocko
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE


|dianyabiao|data_rom4:data4|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
clocko => segment[0][3].CLK1
clocko => segment[0][2].CLK1
clocko => segment[0][1].CLK1
clocko => segment[0][0].CLK1
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT


|dianyabiao|data_rom3:data3
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
address[6] => lpm_rom:lpm_rom_component.address[6]
address[7] => lpm_rom:lpm_rom_component.address[7]
inclock => lpm_rom:lpm_rom_component.inclock
outclock => lpm_rom:lpm_rom_component.outclock
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]


|dianyabiao|data_rom3:data3|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
inclock => altrom:srom.clocki
outclock => altrom:srom.clocko
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE


|dianyabiao|data_rom3:data3|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][3].WADDR6