dianyabiao.vhd.bak

对adc0809的控制及数码管输出

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dianyabiao is
  port (d: in std_logic_vector(7 downto 0); --ADC0809输出的采样数据
		clk,eoc : in std_logic;--clk为系统时钟，eoc为ADC0809转换结束信号
		start,ale,en: out std_logic;--ADC0809控制信号
        abc_in: in std_logic_vector(2 downto 0); --模拟选通信号
		abc_out: out std_logic_vector(2 downto 0);--ADC0809模拟信号选通信号-
		sent: out bit_vector(7 downto 0);
		jiao: out bit_vector(3 downto 0));
end dianyabiao; 

architecture bhv of dianyabiao is 
	component data_rom1
		PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		outclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
END component;

	component data_rom2
		PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		outclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
END component;

	component data_rom3
		PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		outclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
END component;

	component data_rom4
		PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		outclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
END component;
	
	constant a_0:bit_vector :="11111100";
	constant a_1:bit_vector :="01100000";
	constant a_2:bit_vector :="11011010";
	constant a_3:bit_vector :="11110010";
	constant a_4:bit_vector :="01100110";
	constant a_5:bit_vector :="10110110";
	constant a_6:bit_vector :="10111110";
	constant a_7:bit_vector :="11100000";
	constant a_8:bit_vector :="11111110";
	constant a_9:bit_vector :="11110110";
	constant p_1:bit_vector :="1110";
	constant p_2:bit_vector :="1101";
	constant p_3:bit_vector :="1011";
	constant p_4:bit_vector :="0111";
	type states is ( st0,st1, st2, st3, st4,st5,st6); --定义各状态的子类型
	signal current_state, next_state:states:=st0;
	signal regl :std_logic_vector(7 downto 0);--中间数据寄存信
	signal sp_1a,sp_2a,sp_3a,sp_4a:std_logic_vector(3 downto 0);
	signal sp_1,sp_2,sp_3,sp_4:integer range 0 to 9;
	signal z:STD_LOGIC;
	
	
	
begin
	com:process(current_state,eoc) --规定各种状态的转换方式
	begin
	case current_state is
		when st0=>next_state<=st1;ale<='0';start<='0';en<='0';
		when st1=>next_state<=st2;ale<='1';start<='0';en<='0';
		when st2=>next_state<=st3;ale<='0';start<='1';en<='0';
		when st3=>             ale<='0';start<='0';en<='0';
			if eoc='1' then
				next_state<=st3; --检测EOC的下降沿
			else next_state<=st4;
			end if;    
		when st4=>              ale<='0';start<='0';en<='0';
			if eoc='0' then next_state<=st4; --检测EOC的上升沿
			else next_state<=st5;
			end if;
		when st5=>next_state<=st6;ale<='0';start<='0';en<='1';
		when st6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;
		when others=> next_state<=st0;ale<='0';start<='0';en<='0';
	end case;
	end process;
	
	process(clk)
	begin
	if clk'event and clk='1' then
		current_state <=next_state;
	end if;
	end process;

	abc_out<=abc_in; 		
			
	data4:data_rom4 port map(address=>regl,inclock=>clk,q=>sp_4a,outclock=>clk);		
	data3:data_rom3 port map(address=>regl,inclock=>clk,q=>sp_3a,outclock=>clk);		
	data2:data_rom2 port map(address=>regl,inclock=>clk,q=>sp_2a,outclock=>clk);		
	data1:data_rom1 port map(address=>regl,inclock=>clk,q=>sp_1a,outclock=>clk);
	
	data:process(sp_1a,sp_2a,sp_3a,sp_4a)
	begin
		sp_4<=conv_integer(sp_4a);
		sp_3<=conv_integer(sp_3a);
		sp_2<=conv_integer(sp_2a);
		sp_1<=conv_integer(sp_1a);
	end process;
		
	
	
	
	show:process(clk,sp_1,sp_2,sp_3,sp_4)--数码管显示
		variable a:integer range 0 to 7;
	begin
		 if clk'event and clk'last_value='0' and clk='1' then
			a:=a+1;
			if a=1 then
				if    sp_1=0 then sent<=a_0;jiao<=p_1;
				elsif sp_1=1 then sent<=a_1;jiao<=p_1;
				elsif sp_1=2 then sent<=a_2;jiao<=p_1;
				elsif sp_1=3 then sent<=a_3;jiao<=p_1;
				elsif sp_1=4 then sent<=a_4;jiao<=p_1;
				elsif sp_1=5 then sent<=a_5;jiao<=p_1;
				elsif sp_1=6 then sent<=a_6;jiao<=p_1;
				elsif sp_1=7 then sent<=a_7;jiao<=p_1;
				elsif sp_1=8 then sent<=a_8;jiao<=p_1;
				elsif sp_1=9 then sent<=a_9;jiao<=p_1; 
				end if;
			elsif a=2 then
				if    sp_2=0 then sent<=a_0; jiao<=p_2;
				elsif sp_2=1 then sent<=a_1; jiao<=p_2;
				elsif sp_2=2 then sent<=a_2; jiao<=p_2;
				elsif sp_2=3 then sent<=a_3; jiao<=p_2;
				elsif sp_2=4 then sent<=a_4; jiao<=p_2;
				elsif sp_2=5 then sent<=a_5; jiao<=p_2;
				elsif sp_2=6 then sent<=a_6; jiao<=p_2;
				elsif sp_2=7 then sent<=a_7; jiao<=p_2;
				elsif sp_2=8 then sent<=a_8; jiao<=p_2;
				elsif sp_2=9 then sent<=a_9; jiao<=p_2;
				end if;
			elsif a=3 then
				if 	  sp_3=0 then sent<=a_0; jiao<=p_3;
				elsif sp_3=1 then sent<=a_1; jiao<=p_3;
				elsif sp_3=2 then sent<=a_2; jiao<=p_3;
				elsif sp_3=3 then sent<=a_3; jiao<=p_3;
				elsif sp_3=4 then sent<=a_4; jiao<=p_3;
				elsif sp_3=5 then sent<=a_5; jiao<=p_3;
				elsif sp_3=6 then sent<=a_6; jiao<=p_3;
				elsif sp_3=7 then sent<=a_7; jiao<=p_3;
				elsif sp_3=8 then sent<=a_8; jiao<=p_3;
				elsif sp_3=9 then sent<=a_9; jiao<=p_3;
				end if;
			elsif a=4 then
				if 	  sp_4=0 then sent<=a_0; jiao<=p_4;
				elsif sp_4=1 then sent<=a_1; jiao<=p_4;
				elsif sp_4=2 then sent<=a_2; jiao<=p_4;
				elsif sp_4=3 then sent<=a_3; jiao<=p_4;
				elsif sp_4=4 then sent<=a_4; jiao<=p_4;
				elsif sp_4=5 then sent<=a_5; jiao<=p_4;
				elsif sp_4=6 then sent<=a_6; jiao<=p_4;
				elsif sp_4=7 then sent<=a_7; jiao<=p_4;
				elsif sp_4=8 then sent<=a_8; jiao<=p_4;
				elsif sp_4=9 then sent<=a_9; jiao<=p_4;
				end if;
			elsif a=5 then
			    a:=0;
			else
			   null;
			end if;
		end if;
	end process;
	
end bhv;