📄 dianyabiao.map.rpt
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |dianyabiao ; 15 (15) ; 14 ; 0 ; 31 ; 1 (1) ; 2 (2) ; 12 (12) ; 0 (0) ; 0 (0) ; |dianyabiao ; work ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |dianyabiao|current_state ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name ; current_state.st6 ; current_state.st5 ; current_state.st4 ; current_state.st3 ; current_state.st2 ; current_state.st1 ; current_state.st0 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; current_state.st0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; current_state.st1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; current_state.st2 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; current_state.st3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; current_state.st4 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; current_state.st5 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; current_state.st6 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; sent[0]~reg0 ; Stuck at GND due to stuck port data_in ;
; sent[1]~reg0 ; Stuck at VCC due to stuck port data_in ;
; sent[2]~reg0 ; Stuck at GND due to stuck port data_in ;
; sent[3]~reg0 ; Stuck at GND due to stuck port data_in ;
; sent[4]~reg0 ; Stuck at VCC due to stuck port data_in ;
; sent[5]~reg0 ; Stuck at VCC due to stuck port data_in ;
; sent[6]~reg0 ; Stuck at VCC due to stuck port data_in ;
; sent[7]~reg0 ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 8 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 14 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: data_rom4:data4|lpm_rom:lpm_rom_component ;
+------------------------+------------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+------------+--------------------------------------------------+
; LPM_WIDTH ; 4 ; Signed Integer ;
; LPM_WIDTHAD ; 8 ; Signed Integer ;
; LPM_NUMWORDS ; 256 ; Untyped ;
; LPM_ADDRESS_CONTROL ; REGISTERED ; Untyped ;
; LPM_OUTDATA ; REGISTERED ; Untyped ;
; LPM_FILE ; rom_4.hex ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+------------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: data_rom3:data3|lpm_rom:lpm_rom_component ;
+------------------------+------------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+------------+--------------------------------------------------+
; LPM_WIDTH ; 4 ; Signed Integer ;
; LPM_WIDTHAD ; 8 ; Signed Integer ;
; LPM_NUMWORDS ; 256 ; Untyped ;
; LPM_ADDRESS_CONTROL ; REGISTERED ; Untyped ;
; LPM_OUTDATA ; REGISTERED ; Untyped ;
; LPM_FILE ; rom_3.hex ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+------------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: data_rom2:data2|lpm_rom:lpm_rom_component ;
+------------------------+------------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+------------+--------------------------------------------------+
; LPM_WIDTH ; 4 ; Signed Integer ;
; LPM_WIDTHAD ; 8 ; Signed Integer ;
; LPM_NUMWORDS ; 256 ; Untyped ;
; LPM_ADDRESS_CONTROL ; REGISTERED ; Untyped ;
; LPM_OUTDATA ; REGISTERED ; Untyped ;
; LPM_FILE ; rom_2.hex ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+------------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: data_rom1:data1|lpm_rom:lpm_rom_component ;
+------------------------+------------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+------------+--------------------------------------------------+
; LPM_WIDTH ; 4 ; Signed Integer ;
; LPM_WIDTHAD ; 8 ; Signed Integer ;
; LPM_NUMWORDS ; 256 ; Untyped ;
; LPM_ADDRESS_CONTROL ; REGISTERED ; Untyped ;
; LPM_OUTDATA ; REGISTERED ; Untyped ;
; LPM_FILE ; rom_1.hex ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+------------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sun May 24 08:53:42 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianyabiao -c dianyabiao
Info: Found 2 design units, including 1 entities, in source file dianyabiao.vhd
Info: Found design unit 1: dianyabiao-bhv
Info: Found entity 1: dianyabiao
Info: Found 2 design units, including 1 entities, in source file data_rom2.vhd
Info: Found design unit 1: data_rom2-SYN
Info: Found entity 1: data_rom2
Info: Elaborating entity "dianyabiao" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at dianyabiao.vhd(73): object "sp_1a" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at dianyabiao.vhd(73): object "sp_2a" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at dianyabiao.vhd(73): object "sp_3a" assigned a value but never read
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