ml675001.s

oki ml670003 program that sends 1 to uart

.global	SSIOTSCON
.equ SSIOTSCON,   (SSIO_BASE+0x14)    /* SSIO test control register (RW,8,0x00) */

/* bit field of SSIOBUF register */
.global	SSIOSTA_DUMMY
.equ SSIOSTA_DUMMY,   (0xFF)

/* bit field of SSIOST register */
.global	SSIOSTA_BUSY
.equ SSIOSTA_BUSY,    (0x01)  /* transmiting/receiving buffer busy */
.global	SSIOSTA_OERR
.equ SSIOSTA_OERR,    (0x02)  /* overrun error */

/* bit field of SSIOINT register */
.global	SSIOCON_TXCMP
.equ SSIOCON_TXCMP,   (0x01)  /* transmit complete */
.global	SSIOCON_RXCMP
.equ SSIOCON_RXCMP,   (0x02)  /* receive complete */
.global	SSIOCON_TREMP
.equ SSIOCON_TREMP,   (0x04)  /* transmit empty */

/* bit field of SSIOINTEN register */
.global	SSIOCON_TXCMPEN
.equ SSIOCON_TXCMPEN, (0x01)  /* transmit complete enable */
.global	SSIOCON_RXCMPEN
.equ SSIOCON_RXCMPEN, (0x02)  /* receive complete enable */
.global	SSIOCON_TREMPEN
.equ SSIOCON_TREMPEN, (0x04)  /* transmit empty enable */

/* bit field of SSIOCON register */
.global	SSIOCON_SLLSB
.equ SSIOCON_SLLSB,   (0x00)  /* LSB */
.global	SSIOCON_SLMSB
.equ SSIOCON_SLMSB,   (0x20)  /* MSB */
.global	SSIOCON_SLAVE
.equ SSIOCON_SLAVE,   (0x10)  /* Slave */
.global	SSIOCON_MASTER
.equ SSIOCON_MASTER,  (0x00)  /* Master */
.global	SSIOCON_8CCLK
.equ SSIOCON_8CCLK,   (0x00)  /* 1/8CCLK */
.global	SSIOCON_16CCLK
.equ SSIOCON_16CCLK,  (0x01)  /* 1/16CCLK */
.global	SSIOCON_32CCLK
.equ SSIOCON_32CCLK,  (0x02)  /* 1/32CCLK */

/* bit field of SSIOTSCON register */
.global	SSIOTSCON_LBTST
.equ SSIOTSCON_LBTST, (0x80)  /* loop back test mode on*/
.global	SSIOTSCON_NOTST
.equ SSIOTSCON_NOTST, (0x00)  /* test mode off */

/*****************************************************/
/*    I2C control register                          */
/*****************************************************/
.global	I2C_BASE
.equ I2C_BASE,    (0xB7800000)    /* base address */
.global	I2CCON
.equ I2CCON,      (I2C_BASE+0x00) /* I2C control register (RW,8,0x00) */
.global	I2CSAD
.equ I2CSAD,      (I2C_BASE+0x04) /* I2C slave address mode setting register (RW,8,0x00) */
.global	I2CCLR
.equ I2CCLR,      (I2C_BASE+0x08) /* I2C transmit speed setting register (RW,8,0x00) */
.global	I2CSR
.equ I2CSR,       (I2C_BASE+0x0C) /* I2C status register (R,8,0x00) */
.global	I2CIR
.equ I2CIR,       (I2C_BASE+0x10) /* I2C interrupt demand register (RW,8,0x00) */
.global	I2CIMR
.equ I2CIMR,      (I2C_BASE+0x14) /* I2C interrupt mask register  (RW,8,0x00) */
.global	I2CDR
.equ I2CDR,       (I2C_BASE+0x18) /* I2C transmiting/receiving buffer register (RW,8,0x00) */
.global	I2CBC
.equ I2CBC,       (I2C_BASE+0x1C) /* I2C transmit speed setting register (RW,8,0x00) */

/* bit field of I2CCON register */
.global	I2CCON_EN
.equ I2CCON_EN,       (0x01)  /* restart sequence start */
.global	I2CCON_OC
.equ I2CCON_OC,       (0x02)  /* I2C-bus hold */
.global	I2CCON_STCM
.equ I2CCON_STCM,     (0x04)  /* communication start */
.global	I2CCON_RESTR
.equ I2CCON_RESTR,    (0x08)  /* carry out restart */
.global	I2CCON_START
.equ I2CCON_START,    (0x10)  /* exist START byte */

/* bit field of I2CSAD register */
.global	I2CSAD_RW_SND
.equ I2CSAD_RW_SND,   (0x00)  /* data transmiting mode */
.global	I2CSAD_RW_REC
.equ I2CSAD_RW_REC,   (0x01)  /* data receiving mode */

/* bit field of I2CCLR register */
.global	I2CCLR_CMD1
.equ I2CCLR_CMD1, (0x00)  /* Standard-mode */
.global	I2CCLR_CMD4
.equ I2CCLR_CMD4, (0x01)  /* Fast-mode */

/* bit field of I2CSR register */
.global	I2CSR_DAK
.equ I2CSR_DAK,   (0x01)  /* data ACKnowledge no receive */
.global	I2CSR_AAK
.equ I2CSR_AAK,   (0x02)  /* slave address ACKnowledge no receive */

/* bit field of I2CIR register */
.global	I2CIR_IR
.equ I2CIR_IR,    (0x01)  /* interrupt demand */

/* bit field of I2CIMR register */
.global	I2CIMR_MF
.equ I2CIMR_MF,   (0x01)  /* interrupt mask set */

/* bit field of I2CDR register */

/* bit field of I2CBC register */
.global	I2CBC_100K60
.equ I2CBC_100K60,    (0x4B)  /* HCLK=60MHz,I2CMD=100kHz */
.global	I2CBC_400K60
.equ I2CBC_400K60,    (0x13)  /* HCLK=60MHz,I2CMD=400kHz */
.global	I2CBC_100K33
.equ I2CBC_100K33,    (0x2A)  /* HCLK=33MHz,I2CMD=100kHz */
.global	I2CBC_400K33
.equ I2CBC_400K33,    (0x0B)  /* HCLK=33MHz,I2CMD=400kHz */
.global	I2CBC_100K25
.equ I2CBC_100K25,    (0x20)  /* HCLK=25MHz,I2CMD=100kHz */
.global	I2CBC_400K25
.equ I2CBC_400K25,    (0x08)  /* HCLK=25MHz,I2CMD=400kHz */
.global	I2CBC_100K20
.equ I2CBC_100K20,    (0x19)  /* HCLK=20MHz,I2CMD=100kHz */
.global	I2CBC_400K20
.equ I2CBC_400K20,    (0x07)  /* HCLK=20MHz,I2CMD=400kHz */


/*---------------------------------- ML675001 ------------------------------------*/
/*****************************************************/
/*    cache control register                         */
/*****************************************************/
.global	CACHE_BASE
.equ CACHE_BASE,  (0x78200000)        /* base address */
.global	CON
.equ CON,         (CACHE_BASE+0x04)   /* cache control register */
.global	CACHE
.equ CACHE,       (CACHE_BASE+0x08)   /* cachable register */
.global	FLUSH
.equ FLUSH,       (CACHE_BASE+0x1C)   /* FLUSH register */

/* bit field of CON register */
.global	CON_WAY0
.equ CON_WAY0,    (0x00000000)    /* select Way0 (LCK bits) */
.global	CON_WAY1
.equ CON_WAY1,    (0x10000000)    /* select Way1 (LCK bits) */
.global	CON_WAY2
.equ CON_WAY2,    (0x20000000)    /* select Way2 (LCK bits) */
.global	CON_WAY3
.equ CON_WAY3,    (0x30000000)    /* select Way3 (LCK bits) */
.global	CON_LOAD
.equ CON_LOAD,    (0x08000000)    /* Load mode (F bit) */
.global	CON_LOCK0
.equ CON_LOCK0,   (0x00000000)    /* lock 0 Way (BNK bits) */
.global	CON_LOCK1
.equ CON_LOCK1,   (0x02000000)    /* lock 1 Way (BNK bits) */
.global	CON_LOCK2
.equ CON_LOCK2,   (0x04000000)    /* lock 2 Ways (BNK bits) */
.global	CON_LOCK3
.equ CON_LOCK3,   (0x06000000)    /* lock 3 Ways (BNK bits) */

/* bit field of CACHE register */
.global	CACHE_BANK0
.equ CACHE_BANK0,     (0x00010000)    /* Bank0  : Cache enable */
.global	CACHE_BANK8
.equ CACHE_BANK8,     (0x00000001)    /* Bank8  : Cache enable */
.global	CACHE_BANK9
.equ CACHE_BANK9,     (0x00000002)    /* Bank9  : Cache enable */
.global	CACHE_BANK10
.equ CACHE_BANK10,    (0x00000004)    /* Bank10 : Cache enable */
.global	CACHE_BANK11
.equ CACHE_BANK11,    (0x00000008)    /* Bank11 : Cache enable */
.global	CACHE_BANK12
.equ CACHE_BANK12,    (0x00000010)    /* Bank12 : Cache enable */
.global	CACHE_BANK13
.equ CACHE_BANK13,    (0x00000020)    /* Bank13 : Cache enable */
.global	CACHE_BANK24
.equ CACHE_BANK24,    (0x00000100)    /* Bank24 : Cache enable */
.global	CACHE_BANK25
.equ CACHE_BANK25,    (0x00000200)    /* Bank25 : Cache enable */
.global	CACHE_BANK26
.equ CACHE_BANK26,    (0x00000400)    /* Bank26 : Cache enable */
.global	CACHE_BANK27
.equ CACHE_BANK27,    (0x00000800)    /* Bank27 : Cache enable */
.global	CACHE_BANK28
.equ CACHE_BANK28,    (0x00001000)    /* Bank28 : Cache enable */
.global	CACHE_BANK29
.equ CACHE_BANK29,    (0x00002000)    /* Bank29 : Cache enable */

/* bit field of FLUSH register */
.global	FLUSH_FLUSH
.equ FLUSH_FLUSH, (0x00000001)    /* flush cache memory */

/* bit field of DEBUG register */



/*****************************************************/
/*    Chip configuration register                    */
/*****************************************************/
.global	CCR_BASE
.equ CCR_BASE,    (0xB7000000)    /* base address */
.global	GPCTL
.equ GPCTL,       (CCR_BASE+0x00) /* port function control register (RW,16,0x0000) */
.global	BCKCTL
.equ BCKCTL,      (CCR_BASE+0x04) /* clock control register (RW,16,0x0000) */
.global	CSSW
.equ CSSW,        (CCR_BASE+0x08) /* external ROM/RAM chip cell control register (RW,16,0x0000) */
.global	ROMSEL
.equ ROMSEL,      (CCR_BASE+0x0C) /* ROM select register (RW,8,0x00) */

/* bit field of GPCTL */
.global	GPCTL_GPCTL
.equ GPCTL_GPCTL,     (0x7FFF)    /* GPCTL[14:0] */
.global	GPCTL_UART
.equ GPCTL_UART,      (0x0001)    /* select 2nd function (UART) */
.global	GPCTL_SIO
.equ GPCTL_SIO,       (0x0002)    /* select 2nd function (SIO) */
.global	GPCTL_EXBUS
.equ GPCTL_EXBUS,     (0x0004)    /* select 2nd function (external bus) */
.global	GPCTL_DMA0
.equ GPCTL_DMA0,      (0x0008)    /* select 2nd function (DMA CH0) */
.global	GPCTL_DMA1
.equ GPCTL_DMA1,      (0x0010)    /* select 2nd function (DMA CH1) */
.global	GPCTL_PWM
.equ GPCTL_PWM,       (0x0020)    /* select 2nd function (PWM) */
.global	GPCTL_XWAIT
.equ GPCTL_XWAIT,     (0x0040)    /* select 2nd function (external bus wait input) */
.global	GPCTL_XWR
.equ GPCTL_XWR,       (0x0080)    /* select 2nd function (external bus data direction) */
.global	GPCTL_SSIO0
.equ GPCTL_SSIO0,     (0x0100)    /* select 2nd function (SSIO) */
.global	GPCTL_I2C
.equ GPCTL_I2C,       (0x0200)    /* select 2nd function (I2C) */
.global	GPCTL_EXINT0
.equ GPCTL_EXINT0,    (0x0400)    /* select 2nd function (EXINT0) */
.global	GPCTL_EXINT1
.equ GPCTL_EXINT1,    (0x0800)    /* select 2nd function (EXINT1) */
.global	GPCTL_EXINT2
.equ GPCTL_EXINT2,    (0x1000)    /* select 2nd function (EXINT2) */
.global	GPCTL_EXINT3
.equ GPCTL_EXINT3,    (0x2000)    /* select 2nd function (EXINT3) */
.global	GPCTL_EFIQ_N
.equ GPCTL_EFIQ_N,    (0x4000)    /* select 2nd function (EFIQ_N) */

/* bit field of BCKCTL */
.global	BCKCTL_AD
.equ BCKCTL_AD,   (0x0001)    /* ADC */
.global	BCKCTL_PWM
.equ BCKCTL_PWM,  (0x0002)    /* PWM */
.global	BCKCTL_ART0
.equ BCKCTL_ART0, (0x0004)    /* auto reload timer(CH0) */
.global	BCKCTL_ART1
.equ BCKCTL_ART1, (0x0008)    /* auto reload timer(CH1) */
.global	BCKCTL_ART2
.equ BCKCTL_ART2, (0x0010)    /* auto reload timer(CH2) */
.global	BCKCTL_ART3
.equ BCKCTL_ART3, (0x0020)    /* auto reload timer(CH3) */
.global	BCKCTL_ART4
.equ BCKCTL_ART4, (0x0040)    /* auto reload timer(CH4) */
.global	BCKCTL_ART5
.equ BCKCTL_ART5, (0x0080)    /* auto reload timer(CH5) */
.global	BCKCTL_DRAM
.equ BCKCTL_DRAM, (0x0100)    /* DRAM controller */
.global	BCKCTL_DMA
.equ BCKCTL_DMA,  (0x0200)    /* DMAC */
.global	BCKCTL_UART
.equ BCKCTL_UART, (0x0400)    /* UART */
.global	BCKCTL_SSIO
.equ BCKCTL_SSIO, (0x0800)    /* SSIO */
.global	BCKCTL_I2C
.equ BCKCTL_I2C,  (0x1000)    /* I2C */

/* bit field of CSSW register */
.global	CSSW_CHG
.equ CSSW_CHG,        (0x0001)    /* CHG bit */
.global	CSSW_CHG_SET
.equ CSSW_CHG_SET,    (0xA5A5)    /* set CHG */
.global	CSSW_CHG_RESET
.equ CSSW_CHG_RESET,  (0x5A5A)    /* reset CHG */


/*****************************************************/
/*    interrupt number                               */
/*****************************************************/
.global	INT_SYSTEM_TIMER
.equ INT_SYSTEM_TIMER,    0
.global	INT_WDT
.equ INT_WDT,             1
.global	INT_IVT
.equ INT_IVT,             2
.global	INT_GPIOA
.equ INT_GPIOA,           4
.global	INT_GPIOB
.equ INT_GPIOB,           5
.global	INT_GPIOC
.equ INT_GPIOC,           6
.global	INT_GPIOD
.equ INT_GPIOD,           7
.global	INT_GPIOE
.equ INT_GPIOE,           7
.global	INT_SOFTIRQ
.equ INT_SOFTIRQ,         8
.global	INT_UART
.equ INT_UART,            9
.global	INT_SIO
.equ INT_SIO,             10
.global	INT_AD
.equ INT_AD,              11
.global	INT_PWM0
.equ INT_PWM0,            12
.global	INT_PWM1
.equ INT_PWM1,            13
.global	INT_SSIO
.equ INT_SSIO,            14
.global	INT_I2C
.equ INT_I2C,             15
.global	INT_TIMER0
.equ INT_TIMER0,          16
.global	INT_TIMER1
.equ INT_TIMER1,          17
.global	INT_TIMER2
.equ INT_TIMER2,          18
.global	INT_TIMER3
.equ INT_TIMER3,          19
.global	INT_TIMER4
.equ INT_TIMER4,          20
.global	INT_TIMER5
.equ INT_TIMER5,          21
.global	INT_EX0
.equ INT_EX0,             22
.global	INT_DMA0
.equ INT_DMA0,