📄 ml675001.s
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.equ DMACSAD1, (DMA_BASE+0x0208) /* Channel 1 Source Address register (RW,32,0x00000000) */
.global DMACDAD1.equ DMACDAD1, (DMA_BASE+0x020C) /* Channel 1 Destination Address register (RW,32,0x00000000) */
.global DMACSIZ1.equ DMACSIZ1, (DMA_BASE+0x0210) /* Channel 1 Transfer Size register (RW,32,0x00000000) */
.global DMACCINT1.equ DMACCINT1, (DMA_BASE+0x0214) /* Channel 1 interrupt Clear register (W,32,--) */
/* bit field of DMAMOD register */
.global DMAMOD_PRI.equ DMAMOD_PRI, (0x00000001) /* PRI bit */
.global DMAMOD_FIX.equ DMAMOD_FIX, (0x00000000) /* Priority of DMA channel : CH0 > CH1 */
.global DMAMOD_RR.equ DMAMOD_RR, (0x00000001) /* Priority of DMA channel : Round robin */
/* bit field of DMASTA register */
.global DMASTA_STA0.equ DMASTA_STA0, (0x00000001) /* Non-transmitted data is in CH0 */
.global DMASTA_STA1.equ DMASTA_STA1, (0x00000002) /* Non-transmitted data is in CH1 */
/* bit field of DMAINT register */
.global DMAINT_IREQ0.equ DMAINT_IREQ0, (0x00000001) /* CH0 interrupt */
.global DMAINT_IREQ1.equ DMAINT_IREQ1, (0x00000002) /* CH1 interrupt */
.global DMAINT_ISTA0.equ DMAINT_ISTA0, (0x00000100) /* CH0 abnormal end */
.global DMAINT_ISTA1.equ DMAINT_ISTA1, (0x00000200) /* CH1 abnormal end */
.global DMAINT_ISTP0.equ DMAINT_ISTP0, (0x00010000) /* CH0 abnormal end situation */
.global DMAINT_ISTP1.equ DMAINT_ISTP1, (0x00020000) /* CH1 abnormal end situation */
/* bit field of DMAMSK0,1 register */
.global DMACMSK_MSK.equ DMACMSK_MSK, (0x00000001) /* Mask */
/* bit field of DMATMOD0,1 register */
.global DMACTMOD_ARQ.equ DMACTMOD_ARQ, (0x00000001) /* Auto request */
.global DMACTMOD_ERQ.equ DMACTMOD_ERQ, (0x00000000) /* External request */
.global DMACTMOD_BYTE.equ DMACTMOD_BYTE, (0x00000000) /* Byte transmission */
.global DMACTMOD_HWORD.equ DMACTMOD_HWORD, (0x00000002) /* Half word transmission */
.global DMACTMOD_WORD.equ DMACTMOD_WORD, (0x00000004) /* Word transmission */
.global DMACTMOD_SFA.equ DMACTMOD_SFA, (0x00000000) /* Source data type(fixed address device) */
.global DMACTMOD_SIA.equ DMACTMOD_SIA, (0x00000008) /* Source data type(incremental address device) */
.global DMACTMOD_DFA.equ DMACTMOD_DFA, (0x00000000) /* Destination data type(fixed address device) */
.global DMACTMOD_DIA.equ DMACTMOD_DIA, (0x00000010) /* Destination data type(incremental address device) */
.global DMACTMOD_BM.equ DMACTMOD_BM, (0x00000000) /* Bus request mode(burst mode) */
.global DMACTMOD_CSM.equ DMACTMOD_CSM, (0x00000020) /* Bus request mode(cycle steal mode) */
.global DMACTMOD_IMK.equ DMACTMOD_IMK, (0x00000040) /* interrupt mask */
/*****************************************************/
/* interrupt control register */
/*****************************************************/
.global EIC_BASE.equ EIC_BASE, (0x7BF00000) /* base address */
.global IRCL.equ IRCL, (EIC_BASE+0x04) /* Extended interrupt Clear register (W,32,--) */
.global IRQA.equ IRQA, (EIC_BASE+0x10) /* Extended interrupt IRQ register (RW,32,0x00000000) */
.global IDM.equ IDM, (EIC_BASE+0x14) /* Extended interrupt Mode control register (RW,32,0x00000000) */
.global ILC.equ ILC, (EIC_BASE+0x18) /* Extended interrupt IRQ Level control register
(RW,32,0x00000000) */
/* bit field of IRCL register */
.global IRCL_IRCL.equ IRCL_IRCL, (0x0000007F) /* IRCL[6:0] */
/* bit field of IRQA register */
.global IRQA_IRQ16.equ IRQA_IRQ16, (0x00000001) /* IRQ16 */
.global IRQA_IRQ17.equ IRQA_IRQ17, (0x00000002) /* IRQ17 */
.global IRQA_IRQ18.equ IRQA_IRQ18, (0x00000004) /* IRQ18 */
.global IRQA_IRQ19.equ IRQA_IRQ19, (0x00000008) /* IRQ19 */
.global IRQA_IRQ20.equ IRQA_IRQ20, (0x00000010) /* IRQ20 */
.global IRQA_IRQ21.equ IRQA_IRQ21, (0x00000020) /* IRQ21 */
.global IRQA_IRQ22.equ IRQA_IRQ22, (0x00000040) /* IRQ22 */
.global IRQA_IRQ23.equ IRQA_IRQ23, (0x00000080) /* IRQ23 */
.global IRQA_IRQ24.equ IRQA_IRQ24, (0x00000100) /* IRQ24 */
.global IRQA_IRQ25.equ IRQA_IRQ25, (0x00000200) /* IRQ25 */
.global IRQA_IRQ26.equ IRQA_IRQ26, (0x00000400) /* IRQ26 */
.global IRQA_IRQ27.equ IRQA_IRQ27, (0x00000800) /* IRQ27 */
.global IRQA_IRQ28.equ IRQA_IRQ28, (0x00001000) /* IRQ28 */
.global IRQA_IRQ29.equ IRQA_IRQ29, (0x00002000) /* IRQ29 */
.global IRQA_IRQ30.equ IRQA_IRQ30, (0x00004000) /* IRQ30 */
.global IRQA_IRQ31.equ IRQA_IRQ31, (0x00008000) /* IRQ31 */
/* bit field of IDM register */
.global IDM_IDM22.equ IDM_IDM22, (0x00000040) /* IRQ22 */
.global IDM_IDM26.equ IDM_IDM26, (0x00000400) /* IRQ26 */
.global IDM_IDM28.equ IDM_IDM28, (0x00001000) /* IRQ28 */
.global IDM_IDM30.equ IDM_IDM30, (0x00004000) /* IRQ31 */
.global IDM_IDMP22.equ IDM_IDMP22, (0x00000080) /* IRQ22 */
.global IDM_IDMP26.equ IDM_IDMP26, (0x00000800) /* IRQ26 */
.global IDM_IDMP28.equ IDM_IDMP28, (0x00002000) /* IRQ28 */
.global IDM_IDMP30.equ IDM_IDMP30, (0x00008000) /* IRQ31 */
.global IDM_INT_L_L.equ IDM_INT_L_L, (0x00000000) /* level sensing, interrupt occurs when 'L' */
.global IDM_INT_L_H.equ IDM_INT_L_H, (0x0000AAAA) /* level sensing, interrupt occurs when 'H' */
.global IDM_INT_E_F.equ IDM_INT_E_F, (0x00005555) /* edge sensing, interrupt occurs when falling edge */
.global IDM_INT_E_R.equ IDM_INT_E_R, (0x0000FFFF) /* edge sensing, interrupt occurs when rising edge */
.global IDM_IRQ22.equ IDM_IRQ22, (0x000000C0) /* IRQ22 */
.global IDM_IRQ26.equ IDM_IRQ26, (0x00000C00) /* IRQ26 */
.global IDM_IRQ28.equ IDM_IRQ28, (0x00003000) /* IRQ28 */
.global IDM_IRQ31.equ IDM_IRQ31, (0x0000C000) /* IRQ31 */
/* bit field of ILC register */
.global ILC_INT_LV1.equ ILC_INT_LV1, (0x11111111) /* interrupt level 1 */
.global ILC_INT_LV2.equ ILC_INT_LV2, (0x22222222) /* interrupt level 2 */
.global ILC_INT_LV3.equ ILC_INT_LV3, (0x33333333) /* interrupt level 3 */
.global ILC_INT_LV4.equ ILC_INT_LV4, (0x44444444) /* interrupt level 4 */
.global ILC_INT_LV5.equ ILC_INT_LV5, (0x55555555) /* interrupt level 5 */
.global ILC_INT_LV6.equ ILC_INT_LV6, (0x66666666) /* interrupt level 6 */
.global ILC_INT_LV7.equ ILC_INT_LV7, (0x77777777) /* interrupt level 7 */
.global ILC_ILC16.equ ILC_ILC16, (0x00000007) /* IRQ16, IRQ17 */
.global ILC_ILC18.equ ILC_ILC18, (0x00000070) /* IRQ18, IRQ19 */
.global ILC_ILC20.equ ILC_ILC20, (0x00000700) /* IRQ20, IRQ21 */
.global ILC_ILC22.equ ILC_ILC22, (0x00007000) /* IRQ22, IRQ23 */
.global ILC_ILC24.equ ILC_ILC24, (0x00070000) /* IRQ24, IRQ25 */
.global ILC_ILC26.equ ILC_ILC26, (0x00700000) /* IRQ26, IRQ27 */
.global ILC_ILC28.equ ILC_ILC28, (0x07000000) /* IRQ28, IRQ29 */
.global ILC_ILC30.equ ILC_ILC30, (0x70000000) /* IRQ30, IRQ31 */
/*****************************************************/
/* DRAM control register */
/*****************************************************/
.global DCR_BASE.equ DCR_BASE, (0x78180000) /* base address */
.global DBWC.equ DBWC, (DCR_BASE+0x00) /* DRAM Bus Width control register (RW,32,0x00000000) */
.global DRMC.equ DRMC, (DCR_BASE+0x04) /* DRAM control register (RW,32,0x00000000) */
.global DRPC.equ DRPC, (DCR_BASE+0x08) /* DRAM Attribute parameter Setup register (RW,32,0x00000000)*/
.global SDMD.equ SDMD, (DCR_BASE+0x0C) /* SDRAM Mode Setup register (RW,32,0x00000001) */
.global DCMD.equ DCMD, (DCR_BASE+0x10) /* DRAM Command register (RW,32,0x00000000) */
.global RFSH0.equ RFSH0, (DCR_BASE+0x14) /* DRAM Refresh Cycle register 0 (RW,32,0x00000000) */
.global PDWC.equ PDWC, (DCR_BASE+0x18) /* Power Down Mode control register (RW,32,0x00000003) */
.global RFSH1.equ RFSH1, (DCR_BASE+0x1C) /* DRAM Refresh Cycle register 1 (RW,32,0x00000000) */
/* bit field of DBWC register */
.global DBWC_DBDRAM0.equ DBWC_DBDRAM0, (0x00000000) /* DRAM disable */
.global DBWC_DBDRAM8.equ DBWC_DBDRAM8, (0x00000001) /* 8bit width */
.global DBWC_DBDRAM16.equ DBWC_DBDRAM16, (0x00000002) /* 16bit width */
/* bit field of DRMC register */
.global DRMC_8bit.equ DRMC_8bit, (0x00000000) /* DRAM column length : 8bit */
.global DRMC_9bit.equ DRMC_9bit, (0x00000001) /* DRAM column length : 9bit */
.global DRMC_10bit.equ DRMC_10bit, (0x00000002) /* DRAM column length : 10bit */
.global DRMC_SDRAM.equ DRMC_SDRAM, (0x00000000) /* DRAM architecture : SDRAM */
.global DRMC_EDO.equ DRMC_EDO, (0x00000004) /* DRAM architecture : EDO-DRAM */
.global DRMC_2CLK.equ DRMC_2CLK, (0x00000000) /* SDRAM pre-charge latency : 2clock */
.global DRMC_CAS.equ DRMC_CAS, (0x00000010) /* SDRAM pre-charge latency : same as CAS latency */
.global DRMC_PD_DIS.equ DRMC_PD_DIS, (0x00000000) /* automatic shift to SDRAM power down mode : disable */
.global DRMC_PD_EN.equ DRMC_PD_EN, (0x00000040) /* automatic shift to SDRAM power down mode : enable */
.global DRMC_CBR_STOP.equ DRMC_CBR_STOP, (0x00000000) /* CBR refresh : stop */
.global DRMC_CBR_EXE.equ DRMC_CBR_EXE, (0x00000080) /* CBR refresh : execution */
/* bit field of DRPC register */
.global DRPC_DRAMSPEC.equ DRPC_DRAMSPEC, (0x0000000F) /* DRAMSPEC[3:0] */
/* bit field of SDMD register */
.global SDMD_CL2.equ SDMD_CL2, (0x00000000) /* SDRAM CAS latency : 2 */
.global SDMD_CL3.equ SDMD_CL3, (0x00000001) /* SDRAM CAS latency : 3 */
.global SDMD_MODEWR.equ SDMD_MODEWR, (0x00000080) /* setting operation : valid */
/* bit field of DCMD register */
.global DCMD_S_NOP.equ DCMD_S_NOP, (0x00000000) /* No operation */
.global DCMD_S_PALL.equ DCMD_S_PALL, (0x00000004) /* SDRAM all bank pre-charge command */
.global DCMD_S_REF.equ DCMD_S_REF, (0x00000005) /* SDRAM CBR refresh command */
.global DCMD_S_SELF.equ DCMD_S_SELF, (0x00000006) /* SDRAM self refresh start command */
.global DCMD_S_SREX.equ DCMD_S_SREX, (0x00000007) /* SDRAM self refresh stop command */
.global DCMD_EDO_NOP.equ DCMD_EDO_NOP, (0x00000000) /* No operation */
.global DCMD_EDO_PC.equ DCMD_EDO_PC, (0x00000004) /* EDO-DRAM pre-charge cycle */
.global DCMD_EDO_REF.equ DCMD_EDO_REF, (0x00000005) /* EDO-DRAM CBR refresh cycle */
.global DCMD_EDO_SELF.equ DCMD_EDO_SELF, (0x00000006) /* EDO-DRAM self refresh start cycle */
.global DCMD_EDO_SREX.equ DCMD_EDO_SREX, (0x00000007) /* EDO-DRAM self refresh stop cycle */
/* bit field of RFSH0 register */
.global RFSH0_RCCON.equ RFSH0_RCCON, (0x00000001) /* RCCON bit, refresh frequency = refclk(RFSH1)*2(RCCON=0) */
.global RFSH0_SINGLE.equ RFSH0_SINGLE, (0x00000000) /* RCCON bit, refresh frequency = refclk(RFSH1) (RCCON=1) */
/* bit field of RFSH1 register */
.global RFSH1_RFSEL1.equ RFSH1_RFSEL1, (0x000007FF) /* RFSEL1[10:0], refckl(RFSH1) = CCLK/RFSEL1[10:0] */
/* bit field of PDWC register */
.global PDWC_1.equ PDWC_1, (0x00000000) /* when 1 or more cycles of idol state continue,
it shifts to power down mode. */
.global PDWC_2.equ PDWC_2, (0x00000001) /* : */
.global PDWC_3.equ PDWC_3, (0x00000002) /* : */
.global PDWC_4.equ PDWC_4, (0x00000003) /* : */
.global PDWC_5.equ PDWC_5, (0x00000004) /* : */
.global PDWC_6.equ PDWC_6, (0x00000005) /* : */
.global PDWC_7.equ PDWC_7, (0x00000006) /* : */
.global PDWC_8.equ PDWC_8, (0x00000007) /* : */
.global PDWC_9.equ PDWC_9, (0x00000008) /* : */
.global PDWC_10.equ PDWC_10, (0x00000009) /* : */
.global PDWC_11.equ PDWC_11, (0x0000000A) /* : */
.global PDWC_12.equ PDWC_12, (0x0000000B) /* : */
.global PDWC_13.equ PDWC_13, (0x0000000C) /* : */
.global PDWC_14.equ PDWC_14, (0x0000000D) /* : */
.global PDWC_15.equ PDWC_15, (0x0000000E) /* : */
.global PDWC_16.equ PDWC_16, (0x0000000F) /* when 16 or more cycles of idol state continue,
it shifts to power down mode. */
/*****************************************************/
/* SSIO control register */
/*****************************************************/
.global SSIO_BASE.equ SSIO_BASE, (0xB7B01000) /* base address */
.global SSIOBUF.equ SSIOBUF, (SSIO_BASE+0x00) /* transmiting/receiving buffer register (RW,8,0x00) */
.global SSIOST.equ SSIOST, (SSIO_BASE+0x04) /* SSIO status register (RW,8,0x00) */
.global SSIOINT.equ SSIOINT, (SSIO_BASE+0x08) /* SSIO interrupt demand register (RW,8,0x00) */
.global SSIOINTEN.equ SSIOINTEN, (SSIO_BASE+0x0C) /* SSIO interrupt enable register (RW,8,0x00) */
.global SSIOCON.equ SSIOCON, (SSIO_BASE+0x10) /* SSIO control register (RW,8,0x00) */
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