ml675001.s

oki ml670003 program that sends 1 to uart

.global	UARTMSR_TERI
.equ UARTMSR_TERI,    (0x04)  /* trailing edge of ring endicator */
.global	UARTMSR_DDCD
.equ UARTMSR_DDCD,    (0x08)  /* delta data carrer detect */
.global	UARTMSR_CTS
.equ UARTMSR_CTS,     (0x10)  /* clear to send */
.global	UARTMSR_DSR
.equ UARTMSR_DSR,     (0x20)  /* data set ready */
.global	UARTMSR_RI
.equ UARTMSR_RI,      (0x40)  /* ring indicator */
.global	UARTMSR_DCD
.equ UARTMSR_DCD,     (0x80)  /* data carrer detect */

/* bit field of UARTSCR register */
.global	UARTSCR_SCR
.equ UARTSCR_SCR, (0xFF)  /* SCR[7:0] */

/* bit field of UARTDLL register */
.global	UARTDLL_DLL
.equ UARTDLL_DLL, (0xFF)  /* DLL[7:0](=DL[7:0]) */

/* bit field of UARTDLM register */
.global	UARTDLM_DLM
.equ UARTDLM_DLM, (0xFF)  /* DLM[7:0](=DL[15:8]) */


/*****************************************************/
/*    PWM control register                           */
/*****************************************************/
.global	PWM_BASE
.equ PWM_BASE,    (0xB7D00000)    /* base address */
.global	PWR0
.equ PWR0,        (PWM_BASE+0x00) /* PWM register 0 (RW,16,0x0000) */
.global	PWCY0
.equ PWCY0,       (PWM_BASE+0x04) /* PWM cycle register 0 (RW,16,0x0000) */
.global	PWC0
.equ PWC0,        (PWM_BASE+0x08) /* PWM counter 0 (RW,16,0x0000) */
.global	PWCON0
.equ PWCON0,      (PWM_BASE+0x0C) /* PWM contrlo register 0 (RW,16,0x0000) */
.global	PWR1
.equ PWR1,        (PWM_BASE+0x20) /* PWM register 1 (RW,16,0x0000) */
.global	PWCY1
.equ PWCY1,       (PWM_BASE+0x24) /* PWM cycle register 1 (RW,16,0x0000) */
.global	PWC1
.equ PWC1,        (PWM_BASE+0x28) /* PWM counter 1 (RW,16,0x0000) */
.global	PWCON1
.equ PWCON1,      (PWM_BASE+0x2C) /* PWM contrlo register 1 (RW,16,0x0000) */
.global	PWINTSTS
.equ PWINTSTS,    (PWM_BASE+0x3C) /* PWM interrupt status register (RW,16,0x0000) */

/* bit field of PWCON0,1 register */
.global	PWCON_PWR
.equ PWCON_PWR,   (0x0001)    /* enable PWC */
.global	PWCON_CLK1
.equ PWCON_CLK1,  (0x0000)    /* 1/1 CPUCLK */
.global	PWCON_CLK4
.equ PWCON_CLK4,  (0x0002)    /* 1/4 CPUCLK */
.global	PWCON_CLK16
.equ PWCON_CLK16, (0x0004)    /* 1/16 CPUCLK */
.global	PWCON_CLK32
.equ PWCON_CLK32, (0x0006)    /* 1/32 CPUCLK */
.global	PWCON_INTIE
.equ PWCON_INTIE, (0x0040)    /* enable interrupt */
.global	PWCON_PWCOV
.equ PWCON_PWCOV, (0x0080)    

/* bit field of PWINTSTS register */
.global	PWINTSTS_INT1S
.equ PWINTSTS_INT1S,      (0x0200)    /* CH1 interrupt generated */
.global	PWINTSTS_INT0S
.equ PWINTSTS_INT0S,      (0x0100)    /* CH0 interrupt generated */
.global	PWINTSTS_INT1CLR
.equ PWINTSTS_INT1CLR,    (0x0002)    /* CH1 interrupt clear */
.global	PWINTSTS_INT0CLR
.equ PWINTSTS_INT0CLR,    (0x0001)    /* CH0 interrupt clear */


/*****************************************************/
/*    port control register                           */
/*****************************************************/
.global	PCR_BASE
.equ PCR_BASE,    (0xB7A01000)    /* base address */
.global	GPPOA
.equ GPPOA,       (PCR_BASE+0x00) /* port A output register (RW,16,--) */
.global	GPPIA
.equ GPPIA,       (PCR_BASE+0x04) /* port A input register (R,16,--)*/
.global	GPPMA
.equ GPPMA,       (PCR_BASE+0x08) /* port A Mode register (RW,16,0x0000) */
.global	GPIEA
.equ GPIEA,       (PCR_BASE+0x0C) /* port A interrupt enable (RW,16,0x0000) */
.global	GPIPA
.equ GPIPA,       (PCR_BASE+0x10) /* port A interrupt Polarity (RW,16,0x0000) */
.global	GPISA
.equ GPISA,       (PCR_BASE+0x14) /* port A interrupt Status (RW,16,0x0000) */

.global	GPPOB
.equ GPPOB,       (PCR_BASE+0x20) /* port B Output register (RW,16,--) */
.global	GPPIB
.equ GPPIB,       (PCR_BASE+0x24) /* port B Input register (RW,16,--) */
.global	GPPMB
.equ GPPMB,       (PCR_BASE+0x28) /* port B Mode register (RW,16,0x0000) */
.global	GPIEB
.equ GPIEB,       (PCR_BASE+0x2C) /* port B interrupt enable (RW,16,0x0000) */
.global	GPIPB
.equ GPIPB,       (PCR_BASE+0x30) /* port B interrupt Polarity (RW,16,0x0000) */
.global	GPISB
.equ GPISB,       (PCR_BASE+0x34) /* port B interrupt Status (RW,16,0x0000) */

.global	GPPOC
.equ GPPOC,       (PCR_BASE+0x40) /* port C Output register (RW,16,--) */
.global	GPPIC
.equ GPPIC,       (PCR_BASE+0x44) /* port C Input register (RW,16,--) */
.global	GPPMC
.equ GPPMC,       (PCR_BASE+0x48) /* port C Mode register (RW,16,0x0000) */
.global	GPIEC
.equ GPIEC,       (PCR_BASE+0x4C) /* port C interrupt enable (RW,16,0x0000) */
.global	GPIPC
.equ GPIPC,       (PCR_BASE+0x50) /* port C interrupt Polarity (RW,16,0x0000) */
.global	GPISC
.equ GPISC,       (PCR_BASE+0x54) /* port C interrupt Status (RW,16,0x0000) */

.global	GPPOD
.equ GPPOD,       (PCR_BASE+0x60) /* port D Output register (RW,16,--) */
.global	GPPID
.equ GPPID,       (PCR_BASE+0x64) /* port D Input register (RW,16,--) */
.global	GPPMD
.equ GPPMD,       (PCR_BASE+0x68) /* port D Mode register (RW,16,0x0000) */
.global	GPIED
.equ GPIED,       (PCR_BASE+0x6C) /* port D interrupt enable (RW,16,0x0000) */
.global	GPIPD
.equ GPIPD,       (PCR_BASE+0x70) /* port D interrupt Polarity (RW,16,0x0000) */
.global	GPISD
.equ GPISD,       (PCR_BASE+0x74) /* port D interrupt Status (RW,16,0x0000) */

.global	GPPOE
.equ GPPOE,       (PCR_BASE+0x80) /* port E Output register (RW,16,--) */
.global	GPPIE
.equ GPPIE,       (PCR_BASE+0x84) /* port E Input register (RW,16,--) */
.global	GPPME
.equ GPPME,       (PCR_BASE+0x88) /* port E Mode register (RW,16,0x0000) */
.global	GPIEE
.equ GPIEE,       (PCR_BASE+0x8C) /* port E interrupt enable (RW,16,0x0000) */
.global	GPIPE
.equ GPIPE,       (PCR_BASE+0x90) /* port E interrupt Polarity (RW,16,0x0000) */
.global	GPISE
.equ GPISE,       (PCR_BASE+0x94) /* port E interrupt Status (RW,16,0x0000) */

/* bit field of GPPOA/GPPOB/GPPOC/GPPOD/GPPOE register */
.global	GPPOA_GPPOA
.equ GPPOA_GPPOA, (0x00FF)    /* GPPOA[7:0] */
.global	GPPOB_GPPOB
.equ GPPOB_GPPOB, (0x00FF)    /* GPPOB[7:0] */
.global	GPPOC_GPPOC
.equ GPPOC_GPPOC, (0x00FF)    /* GPPOC[7:0] */
.global	GPPOD_GPPOD
.equ GPPOD_GPPOD, (0x00FF)    /* GPPOD[7:0] */
.global	GPPOE_GPPOE
.equ GPPOE_GPPOE, (0x03FF)    /* GPPOE[9:0] */

/* bit field of GPPIA/GPPIB/GPPIC/GPPID/GPPIE register */
.global	GPPIA_GPPIA
.equ GPPIA_GPPIA, (0x00FF)    /* GPPIA[7:0] */
.global	GPPIB_GPPIB
.equ GPPIB_GPPIB, (0x00FF)    /* GPPIB[7:0] */
.global	GPPIC_GPPIC
.equ GPPIC_GPPIC, (0x00FF)    /* GPPIC[7:0] */
.global	GPPID_GPPID
.equ GPPID_GPPID, (0x00FF)    /* GPPID[7:0] */
.global	GPPIE_GPPIE
.equ GPPIE_GPPIE, (0x03FF)    /* GPPIE[9:0] */

/* bit field of GPPMA/GPPMB/GPPMC/GPPMD/GPPME register */
.global	GPPMA_GPPMA
.equ GPPMA_GPPMA, (0x00FF)    /* GPPMA[7:0] 0:input, 1:output */
.global	GPPMB_GPPMB
.equ GPPMB_GPPMB, (0x00FF)    /* GPPMB[7:0] 0:input, 1:output */
.global	GPPMC_GPPMC
.equ GPPMC_GPPMC, (0x00FF)    /* GPPMC[7:0] 0:input, 1:output */
.global	GPPMD_GPPMD
.equ GPPMD_GPPMD, (0x00FF)    /* GPPMD[7:0] 0:input, 1:output */
.global	GPPME_GPPME
.equ GPPME_GPPME, (0x03FF)    /* GPPME[9:0] 0:input, 1:output */

/* bit field of GPIEA/GPIEB/GPIEC/GPIED/GPIEE register */
.global	GPIEA_GPIEA
.equ GPIEA_GPIEA, (0x00FF)    /* GPIEA[7:0] 0:interrupt disable, 1:interrupt enable */
.global	GPIEB_GPIEB
.equ GPIEB_GPIEB, (0x00FF)    /* GPIEB[7:0] 0:interrupt disable, 1:interrupt enable */
.global	GPIEC_GPIEC
.equ GPIEC_GPIEC, (0x00FF)    /* GPIEC[7:0] 0:interrupt disable, 1:interrupt enable */
.global	GPIED_GPIED
.equ GPIED_GPIED, (0x00FF)    /* GPIED[7:0] 0:interrupt disable, 1:interrupt enable */
.global	GPIEE_GPIEE
.equ GPIEE_GPIEE, (0x03FF)    /* GPIEE[9:0] 0:interrupt disable, 1:interrupt enable */

/* bit field of GPIPA/GPIPB/GPIPC/GPIPD/GPIPE register */
.global	GPIPA_GPIPA
.equ GPIPA_GPIPA, (0x00FF)    /* GPIPA[7:0] 0:falling edge, 1:rising edge */
.global	GPIPB_GPIPB
.equ GPIPB_GPIPB, (0x00FF)    /* GPIPB[7:0] 0:falling edge, 1:rising edge */
.global	GPIPC_GPIPC
.equ GPIPC_GPIPC, (0x00FF)    /* GPIPC[7:0] 0:falling edge, 1:rising edge */
.global	GPIPD_GPIPD
.equ GPIPD_GPIPD, (0x00FF)    /* GPIPD[7:0] 0:falling edge, 1:rising edge */
.global	GPIPE_GPIPE
.equ GPIPE_GPIPE, (0x03FF)    /* GPIPE[9:0] 0:falling edge, 1:rising edge */

/* bit field of GPISA/GPISB/GPISC/GPISD/GPISE register */
.global	GPISA_GPISA
.equ GPISA_GPISA, (0x00FF)    /* GPISA[7:0] 0:interrupt not occurred, 1:interrupt occurred */
.global	GPISB_GPISB
.equ GPISB_GPISB, (0x00FF)    /* GPISB[7:0] 0:interrupt not occurred, 1:interrupt occurred */
.global	GPISC_GPISC
.equ GPISC_GPISC, (0x00FF)    /* GPISC[7:0] 0:interrupt not occurred, 1:interrupt occurred */
.global	GPISD_GPISD
.equ GPISD_GPISD, (0x00FF)    /* GPISD[7:0] 0:interrupt not occurred, 1:interrupt occurred */
.global	GPISE_GPISE
.equ GPISE_GPISE, (0x03FF)    /* GPISE[9:0] 0:interrupt not occurred, 1:interrupt occurred */


/*****************************************************/
/*    ADC control register                           */
/*****************************************************/
.global	ADC_BASE
.equ ADC_BASE,    (0xB6001000)    /* base address */
.global	ADCON0
.equ ADCON0,      (ADC_BASE+0x00) /* ADC control 0 register (RW,16,0x0000) */
.global	ADCON1
.equ ADCON1,      (ADC_BASE+0x04) /* ADC control 1 register (RW,16,0x0000) */
.global	ADCON2
.equ ADCON2,      (ADC_BASE+0x08) /* ADC control 2 register (RW,16,0x0003) */
.global	ADINT
.equ ADINT,       (ADC_BASE+0x0C) /* AD interrupt control register (RW,16,0x0000) */
.global	ADFINT
.equ ADFINT,      (ADC_BASE+0x10) /* AD Forced interrupt register (RW,16,0x0000) */
.global	ADR0
.equ ADR0,        (ADC_BASE+0x14) /* AD Result 0 register (RW,16,0x0000) */
.global	ADR1
.equ ADR1,        (ADC_BASE+0x18) /* AD Result 1 register (RW,16,0x0000) */
.global	ADR2
.equ ADR2,        (ADC_BASE+0x1C) /* AD Result 2 register (RW,16,0x0000) */
.global	ADR3
.equ ADR3,        (ADC_BASE+0x20) /* AD Result 3 register (RW,16,0x0000) */


/* bit field of ADCON0 register */
.global	ADCON0_ADSNM
.equ ADCON0_ADSNM,    (0x0003)    /* ADSNM[1:0] */
.global	ADCON0_CH0_3
.equ ADCON0_CH0_3,    (0x0000)    /* CH0->CH1->CH2->CH3 */
.global	ADCON0_CH1_3
.equ ADCON0_CH1_3,    (0x0001)    /* CH1->CH2->CH3 */
.global	ADCON0_CH2_3
.equ ADCON0_CH2_3,    (0x0002)    /* CH2->CH3 */
.global	ADCON0_CH3_3
.equ ADCON0_CH3_3,    (0x0003)    /* CH3 */
.global	ADCON0_ADRUN
.equ ADCON0_ADRUN,    (0x0010)    /* AD conversion start */
.global	ADCON0_SCNC
.equ ADCON0_SCNC,     (0x0040)    /* Stop after a round */

/* bit field of ADCON1 register */
.global	ADCON1_ADSTM
.equ ADCON1_ADSTM,    (0x0003)    /* ADSTM[1:0] */
.global	ADCON1_CH0
.equ ADCON1_CH0,      (0x0000)    /* CH0 */
.global	ADCON1_CH1
.equ ADCON1_CH1,      (0x0001)    /* CH1 */
.global	ADCON1_CH2
.equ ADCON1_CH2,      (0x0002)    /* CH2 */
.global	ADCON1_CH3
.equ ADCON1_CH3,      (0x0003)    /* CH3 */
.global	ADCON1_STS
.equ ADCON1_STS,      (0x0010)    /* AD conversion start */

/* bit field of ADCON2 register */
.global	ADCON2_ACKSEL
.equ ADCON2_ACKSEL,   (0x0003)    /* ACKSEL[1:0] */
.global	ADCON2_CLK2
.equ ADCON2_CLK2,     (0x0001)    /* CPUCLK/2 */
.global	ADCON2_CLK4
.equ ADCON2_CLK4,     (0x0002)    /* CPUCLK/4 */
.global	ADCON2_CLK8
.equ ADCON2_CLK8,     (0x0003)    /* CPUCLK/8 */

/* bit field of ADINT register */
.global	ADINT_INTSN
.equ ADINT_INTSN,     (0x0001)    /* AD conversion of ch7 finished (scan mode) */
.global	ADINT_INTST
.equ ADINT_INTST,     (0x0002)    /* AD conversion finished (select mode) */
.global	ADINT_ADSNIE
.equ ADINT_ADSNIE,    (0x0004)    /* enable interrupt (scan mode) */
.global	ADINT_ADSTIE
.equ ADINT_ADSTIE,    (0x0008)    /* enable interrupt (select mode) */

/* bit field of ADFINT register */
.global	ADFINT_ADFAS
.equ ADFINT_ADFAS,    (0x0001)    /* Assert interrupt signal */

/* bit field of ADR0,ADR1,ADR2,ADR3 register */
.global	ADR0_DT0
.equ ADR0_DT0,    (0x03FF)    /* DT0[9:0] AD result */
.global	ADR1_DT1
.equ ADR1_DT1,    (0x03FF)    /* DT1[9:0] AD result */
.global	ADR2_DT2
.equ ADR2_DT2,    (0x03FF)    /* DT2[9:0] AD result */
.global	ADR3_DT3
.equ ADR3_DT3,    (0x03FF)    /* DT3[9:0] AD result */


/*****************************************************/
/*    DMA control register                           */
/*****************************************************/
.global	DMA_BASE
.equ DMA_BASE,    (0x7BE00000)        /* base address */
.global	DMAMOD
.equ DMAMOD,      (DMA_BASE+0x0000)   /* DMA Mode register (RW,32,0x00000000) */
.global	DMASTA
.equ DMASTA,      (DMA_BASE+0x0004)   /* DMA Status register (R,32,0x00000000) */
.global	DMAINT
.equ DMAINT,      (DMA_BASE+0x0008)   /* DMA interrupt Status register (R,32,0x00000000) */
.global	DMACMSK0
.equ DMACMSK0,    (DMA_BASE+0x0100)   /* Channel 0 Mask register (RW,32,0x00000001) */
.global	DMACTMOD0
.equ DMACTMOD0,   (DMA_BASE+0x0104)   /* Channel 0 Transfer Mode register (RW,32,0x00000040) */
.global	DMACSAD0
.equ DMACSAD0,    (DMA_BASE+0x0108)   /* Channel 0 Source Address register (RW,32,0x00000000) */
.global	DMACDAD0
.equ DMACDAD0,    (DMA_BASE+0x010C)   /* Channel 0 Destination Address register (RW,32,0x00000000) */
.global	DMACSIZ0
.equ DMACSIZ0,    (DMA_BASE+0x0110)   /* Channel 0 Transfer Size register (RW,32,0x00000000) */
.global	DMACCINT0
.equ DMACCINT0,   (DMA_BASE+0x0114)   /* Channel 0 interrupt Clear register (W,32,--) */
.global	DMACMSK1
.equ DMACMSK1,    (DMA_BASE+0x0200)   /* Channel 1 Mask register (RW,32,0x00000001) */
.global	DMACTMOD1
.equ DMACTMOD1,   (DMA_BASE+0x0204)   /* Channel 1 Transfer Mode register (RW,32,0x00000040) */
.global	DMACSAD1