ml675001.s

oki ml670003 program that sends 1 to uart

.equ SIOBUF_SIOBUF,   (0x00FF)    /* SIOBUF[7:0] */

/* bit field of SIOSTA register */
.global	SIOSTA_FERR
.equ SIOSTA_FERR,     (0x0001)    /* framing error */
.global	SIOSTA_OERR
.equ SIOSTA_OERR,     (0x0002)    /* overrun error */
.global	SIOSTA_PERR
.equ SIOSTA_PERR,     (0x0004)    /* parity error */
.global	SIOSTA_RVIRQ
.equ SIOSTA_RVIRQ,    (0x0010)    /* receive ready */
.global	SIOSTA_TRIRQ
.equ SIOSTA_TRIRQ,    (0x0020)    /* transmit ready */

/* bit field of SIOCON register */
.global	SIOCON_LN7
.equ SIOCON_LN7,      (0x0001)    /* data length : 7bit */
.global	SIOCON_LN8
.equ SIOCON_LN8,      (0x0000)    /* data length : 8bit */
.global	SIOCON_PEN
.equ SIOCON_PEN,      (0x0002)    /* parity enabled */
.global	SIOCON_PDIS
.equ SIOCON_PDIS,     (0x0000)    /* parity disabled */
.global	SIOCON_EVN
.equ SIOCON_EVN,      (0x0004)    /* even parity */
.global	SIOCON_ODD
.equ SIOCON_ODD,      (0x0000)    /* odd parity */
.global	SIOCON_TSTB1
.equ SIOCON_TSTB1,    (0x0008)    /* stop bit : 1 */
.global	SIOCON_TSTB2
.equ SIOCON_TSTB2,    (0x0000)    /* stop bit : 2 */

/* bit field of SIOBCN register */
.global	SIOBCN_BGRUN
.equ SIOBCN_BGRUN,    (0x0010)    /* count start */

/* bit field of SIOBT register */
.global	SIOBT_SIOBT
.equ SIOBT_SIOBT, (0x00FF)    /* SIOBT[7:0] */

/* bit field of SIOTCN register */
.global	SIOTCN_MFERR
.equ SIOTCN_MFERR,    (0x0001)    /* generate framin error */
.global	SIOTCN_MPERR
.equ SIOTCN_MPERR,    (0x0002)    /* generate parity error */
.global	SIOTCN_LBTST
.equ SIOTCN_LBTST,    (0x0080)    /* loop back test */


/*---------------------------------- ML674001 ------------------------------------*/
/*****************************************************/
/*    timer control register                         */
/*****************************************************/
.global	TCR_BASE
.equ TCR_BASE,    (0xB7F00000)    /* base address */
.global	TIMECNTL0
.equ TIMECNTL0,   (TCR_BASE+0x00) /* timer0 control register (RW,16,0x0000) */
.global	TIMEBASE0
.equ TIMEBASE0,   (TCR_BASE+0x04) /* timer0 base register (RW,16,0x0000) */
.global	TIMECNT0
.equ TIMECNT0,    (TCR_BASE+0x08) /* timer0 counter register (R,16,0x0000) */
.global	TIMECMP0
.equ TIMECMP0,    (TCR_BASE+0x0C) /* timer0 compare register (RW,16,0xFFFF) */
.global	TIMESTAT0
.equ TIMESTAT0,   (TCR_BASE+0x10) /* timer0 status register (RW,16,0x0000) */
.global	TIMECNTL1
.equ TIMECNTL1,   (TCR_BASE+0x20) /* timer1 control register (RW,16,0x0000) */
.global	TIMEBASE1
.equ TIMEBASE1,   (TCR_BASE+0x24) /* timer1 base register (RW,16,0x0000) */
.global	TIMECNT1
.equ TIMECNT1,    (TCR_BASE+0x28) /* timer1 counter register (R,16,0x0000) */
.global	TIMECMP1
.equ TIMECMP1,    (TCR_BASE+0x2C) /* timer1 compare register (RW,16,0xFFFF) */
.global	TIMESTAT1
.equ TIMESTAT1,   (TCR_BASE+0x30) /* timer1 status register (RW,16,0x0000) */
.global	TIMECNTL2
.equ TIMECNTL2,   (TCR_BASE+0x40) /* timer2 control register (RW,16,0x0000) */
.global	TIMEBASE2
.equ TIMEBASE2,   (TCR_BASE+0x44) /* timer2 base register (RW,16,0x0000) */
.global	TIMECNT2
.equ TIMECNT2,    (TCR_BASE+0x48) /* timer2 counter register (R,16,0x0000) */
.global	TIMECMP2
.equ TIMECMP2,    (TCR_BASE+0x4C) /* timer2 compare register (RW,16,0xFFFF) */
.global	TIMESTAT2
.equ TIMESTAT2,   (TCR_BASE+0x50) /* timer2 status register (RW,16,0x0000) */
.global	TIMECNTL3
.equ TIMECNTL3,   (TCR_BASE+0x60) /* timer3 control register (RW,16,0x0000) */
.global	TIMEBASE3
.equ TIMEBASE3,   (TCR_BASE+0x64) /* timer3 base register (RW,16,0x0000) */
.global	TIMECNT3
.equ TIMECNT3,    (TCR_BASE+0x68) /* timer3 counter register (R,16,0x0000) */
.global	TIMECMP3
.equ TIMECMP3,    (TCR_BASE+0x6C) /* timer3 compare register (RW,16,0xFFFF) */
.global	TIMESTAT3
.equ TIMESTAT3,   (TCR_BASE+0x70) /* timer3 status register (RW,16,0x0000) */
.global	TIMECNTL4
.equ TIMECNTL4,   (TCR_BASE+0x80) /* timer4 control register (RW,16,0x0000) */
.global	TIMEBASE4
.equ TIMEBASE4,   (TCR_BASE+0x84) /* timer4 base register (RW,16,0x0000) */
.global	TIMECNT4
.equ TIMECNT4,    (TCR_BASE+0x88) /* timer4 counter register (R,16,0x0000) */
.global	TIMECMP4
.equ TIMECMP4,    (TCR_BASE+0x8C) /* timer4 compare register (RW,16,0xFFFF) */
.global	TIMESTAT4
.equ TIMESTAT4,   (TCR_BASE+0x90) /* timer4 status register (RW,16,0x0000) */
.global	TIMECNTL5
.equ TIMECNTL5,   (TCR_BASE+0xA0) /* timer5 control register (RW,16,0x0000) */
.global	TIMEBASE5
.equ TIMEBASE5,   (TCR_BASE+0xA4) /* timer5 base register (RW,16,0x0000) */
.global	TIMECNT5
.equ TIMECNT5,    (TCR_BASE+0xA8) /* timer5 counter register (R,16,0x0000) */
.global	TIMECMP5
.equ TIMECMP5,    (TCR_BASE+0xAC) /* timer5 compare register (RW,16,0xFFFF) */
.global	TIMESTAT5
.equ TIMESTAT5,   (TCR_BASE+0xB0) /* timer5 status register (RW,16,0x0000) */

/* bit field of TIMECNTL0-5 register */
.global	TIMECNTL_CLK
.equ TIMECNTL_CLK,    (0x0000)    /* CPUCLK */
.global	TIMECNTL_CLK2
.equ TIMECNTL_CLK2,   (0x0020)    /* CPUCLK/2 */
.global	TIMECNTL_CLK4
.equ TIMECNTL_CLK4,   (0x0040)    /* CPUCLK/4 */
.global	TIMECNTL_CLK8
.equ TIMECNTL_CLK8,   (0x0060)    /* CPUCLK/8 */
.global	TIMECNTL_CLK16
.equ TIMECNTL_CLK16,  (0x0080)    /* CPUCLK/16 */
.global	TIMECNTL_CLK32
.equ TIMECNTL_CLK32,  (0x00A0)    /* CPUCLK/32 */
.global	TIMECNTL_IE
.equ TIMECNTL_IE,     (0x0010)    /* enable interrupt */
.global	TIMECNTL_START
.equ TIMECNTL_START,  (0x0008)    /* timer start */
.global	TIMECNTL_OS
.equ TIMECNTL_OS,     (0x0001)    /* one shot timer */
.global	TIMECNTL_INT
.equ TIMECNTL_INT,    (0x0000)    /* interval timer */

/* bit field of TIMESTAT0-5 register */
.global	TIMESTAT_STATUS
.equ TIMESTAT_STATUS, (0x0001)    /* status bit */

/*****************************************************/
/*    Watch Dog Timer control register               */
/*****************************************************/
.global	WDT_BASE
.equ WDT_BASE,    (0xB7E00000)    /* base address */
.global	WDTCON
.equ WDTCON,      (WDT_BASE+0x00) /* Watch Dog Timer control register (W,8,--) */
.global	WDTBCON
.equ WDTBCON,     (WDT_BASE+0x04) /* time base counter control register (RW,8,0x00) */
.global	WDSTAT
.equ WDSTAT,      (WDT_BASE+0x14) /* Watch Dog Timer status register (RW,8,0x00) */

/* bit field of WDTCON */
.global	WDTCON_0xC3
.equ WDTCON_0xC3, (0xC3)  /* 0xC3 */
.global	WDTCON_0x3C
.equ WDTCON_0x3C, (0x3C)  /* 0x3C */

/* bit field of WDTBCON */
.global	WDTBCON_CLK32
.equ WDTBCON_CLK32,   (0x00)  /* CPUCLK/32 */
.global	WDTBCON_CLK64
.equ WDTBCON_CLK64,   (0x01)  /* CPUCLK/64 */
.global	WDTBCON_CLK128
.equ WDTBCON_CLK128,  (0x02)  /* CPUCLK/128 */
.global	WDTBCON_CLK256
.equ WDTBCON_CLK256,  (0x03)  /* CPUCLK/256 */
.global	WDTBCON_WDTM
.equ WDTBCON_WDTM,    (0x00)  /* WDT mode */
.global	WDTBCON_ITM
.equ WDTBCON_ITM,     (0x08)  /* interval timer mode */
.global	WDTBCON_ITDIS
.equ WDTBCON_ITDIS,   (0x00)  /* disable interval timer */
.global	WDTBCON_ITEN
.equ WDTBCON_ITEN,    (0x10)  /* enable interval timer */
.global	WDTBCON_INT
.equ WDTBCON_INT,     (0x00)  /* generate interrupt */
.global	WDTBCON_RESET
.equ WDTBCON_RESET,   (0x40)  /* system reset */
.global	WDTBCON_WDHLT
.equ WDTBCON_WDHLT,   (0x80)  /* HALT */
.global	WDTBCON_WE
.equ WDTBCON_WE,      (0x5A)  /* enable writing to this register */

/* bit field of WDTSTAT */
.global	WDSTAT_RSTWDT
.equ WDSTAT_RSTWDT,   (0x01)  /* reset by WDT */
.global	WDSTAT_RSTPWON
.equ WDSTAT_RSTPWON,  (0x00)  /* reset by power on */
.global	WDSTAT_WDTIST
.equ WDSTAT_WDTIST,   (0x10)  /* WDT interrupt */
.global	WDSTAT_IVTIST
.equ WDSTAT_IVTIST,   (0x20)  /* IVT interrupt */


/*****************************************************/
/*    UART control register                          */
/*****************************************************/
.global	UCR_BASE
.equ UCR_BASE,    (0xB7B00000)    /* base address */
.global	UARTRBR
.equ UARTRBR,     (UCR_BASE+0x00) /* receiver buffer register (R,8,--) */
.global	UARTTHR
.equ UARTTHR,     (UCR_BASE+0x00) /* transmitter buffer register (R,8--) */
.global	UARTIER
.equ UARTIER,     (UCR_BASE+0x04) /* interrupt enable register (RW,8,0x00) */
.global	UARTIIR
.equ UARTIIR,     (UCR_BASE+0x08) /* interrupt identification (R,8,0x01) */
.global	UARTFCR
.equ UARTFCR,     (UCR_BASE+0x08) /* FIFO control register (W,8,0x00) */
.global	UARTLCR
.equ UARTLCR,     (UCR_BASE+0x0C) /* line control register (RW,8,0x00) */
.global	UARTMCR
.equ UARTMCR,     (UCR_BASE+0x10) /* modem control register (RW,8,0x00) */
.global	UARTLSR
.equ UARTLSR,     (UCR_BASE+0x14) /* line status register (RW,8,0x60) */
.global	UARTMSR
.equ UARTMSR,     (UCR_BASE+0x18) /* modem status register (RW,8,--) */
.global	UARTSCR
.equ UARTSCR,     (UCR_BASE+0x1C) /* scratchpad register (RW,8,--) */
.global	UARTDLL
.equ UARTDLL,     (UCR_BASE+0x00) /* divisor latch(LSB) (RW,8,0x00) */
.global	UARTDLM
.equ UARTDLM,     (UCR_BASE+0x04) /* divisor latch(MSB) (RW,8,0x00) */

/* bit field of UARTRBR register */
.global	UARTRBR_RBR
.equ UARTRBR_RBR, (0xFF)  /* RBR[7:0] */

/* bit field of UARTTHR register */
.global	UARTTHR_THR
.equ UARTTHR_THR, (0xFF)  /* THR[7:0] */

/* bit field of UARTIER register */
.global	UARTIER_ERBF
.equ UARTIER_ERBF,    (0x01)  /* enable received data available interrupt */
.global	UARTIER_ETBEF
.equ UARTIER_ETBEF,   (0x02)  /* enable transmitter holding register empty interrupt */
.global	UARTIER_ELSI
.equ UARTIER_ELSI,    (0x04)  /* enable receiver line status interrupt */
.global	UARTIER_EDSI
.equ UARTIER_EDSI,    (0x08)  /* enable modem status interrupt */

/* bit field of UARTIIR register */
.global	UARTIIR_IP
.equ UARTIIR_IP,      (0x01)  /* interrupt generated */
.global	UARTIIR_LINE
.equ UARTIIR_LINE,    (0x06)  /* receiver line status interrupt */
.global	UARTIIR_RCV
.equ UARTIIR_RCV,     (0x04)  /* receiver interrupt */
.global	UARTIIR_TO
.equ UARTIIR_TO,      (0x0C)  /* time out interrupt */
.global	UARTIIR_TRA
.equ UARTIIR_TRA,     (0x02)  /* transmitter interrupt */
.global	UARTIIR_FM
.equ UARTIIR_FM,      (0xC0)  /* FIFO mode */

/* bit field of UARTFCR register */
.global	UARTFCR_FE
.equ UARTFCR_FE,      (0x01)  /* FIFO enable */
.global	UARTFCR_FD
.equ UARTFCR_FD,      (0x00)  /* FIFO disable */
.global	UARTFCR_RFCLR
.equ UARTFCR_RFCLR,   (0x02)  /* receiver FIFO clear */
.global	UARTFCR_TFCLR
.equ UARTFCR_TFCLR,   (0x04)  /* transmitter FIFO clear */
.global	UARTFCR_RFLV1
.equ UARTFCR_RFLV1,   (0x00)  /* RCVR FIFO interrupt trigger level : 1byte */
.global	UARTFCR_RFLV4
.equ UARTFCR_RFLV4,   (0x40)  /* RCVR FIFO interrupt trigger level : 4byte */
.global	UARTFCR_RFLV8
.equ UARTFCR_RFLV8,   (0x80)  /* RCVR FIFO interrupt trigger level : 8byte */
.global	UARTFCR_RFLV14
.equ UARTFCR_RFLV14,  (0xC0)  /* RCVR FIFO interrupt trigger level : 14byte */

/* bit field of UARTLCR register */
.global	UARTLCR_LEN5
.equ UARTLCR_LEN5,    (0x00)  /* data length : 5bit */
.global	UARTLCR_LEN6
.equ UARTLCR_LEN6,    (0x01)  /* data length : 6bit */
.global	UARTLCR_LEN7
.equ UARTLCR_LEN7,    (0x02)  /* data length : 7bit */
.global	UARTLCR_LEN8
.equ UARTLCR_LEN8,    (0x03)  /* data length : 8bit */
.global	UARTLCR_STB1
.equ UARTLCR_STB1,    (0x00)  /* stop bit : 1 */
.global	UARTLCR_STB2
.equ UARTLCR_STB2,    (0x04)  /* stop bit : 2(data length 6-8) */
.global	UARTLCR_STB1_5
.equ UARTLCR_STB1_5,  (0x04)  /* stop bit : 1.5(data length 5) */
.global	UARTLCR_PEN
.equ UARTLCR_PEN,     (0x08)  /* parity enabled */
.global	UARTLCR_PDIS
.equ UARTLCR_PDIS,    (0x00)  /* parity disabled */
.global	UARTLCR_EVN
.equ UARTLCR_EVN,     (0x10)  /* even parity */
.global	UARTLCR_ODD
.equ UARTLCR_ODD,     (0x00)  /* odd parity */
.global	UARTLCR_SP
.equ UARTLCR_SP,      (0x20)  /* stick parity */
.global	UARTLCR_BRK
.equ UARTLCR_BRK,     (0x40)  /* break delivery */
.global	UARTLCR_DLAB
.equ UARTLCR_DLAB,    (0x80)  /* devisor latch access bit */

/* bit field of UARTMCR register */
.global	UARTMCR_DTR
.equ UARTMCR_DTR,     (0x01)  /* data terminal ready */
.global	UARTMCR_RTS
.equ UARTMCR_RTS,     (0x02)  /* request to send */
.global	UARTMCR_LOOP
.equ UARTMCR_LOOP,    (0x10)  /* loopback */

/* bit field of UARTLSR register */
.global	UARTLSR_DR
.equ UARTLSR_DR,      (0x01)  /* data ready */
.global	UARTLSR_OE
.equ UARTLSR_OE,      (0x02)  /* overrun error */
.global	UARTLSR_PE
.equ UARTLSR_PE,      (0x04)  /* parity error */
.global	UARTLSR_FE
.equ UARTLSR_FE,      (0x08)  /* framing error */
.global	UARTLSR_BI
.equ UARTLSR_BI,      (0x10)  /* break interrupt */
.global	UARTLSR_THRE
.equ UARTLSR_THRE,    (0x20)  /* transmitter holding register empty */
.global	UARTLSR_TEMT
.equ UARTLSR_TEMT,    (0x40)  /* transmitter empty */
.global	UARTLSR_ERF
.equ UARTLSR_ERF,     (0x80)  /* receiver FIFO error */

/* bit field of UARTMSR register */
.global	UARTMSR_DCTS
.equ UARTMSR_DCTS,    (0x01)  /* delta clear to send */
.global	UARTMSR_DDSR
.equ UARTMSR_DDSR,    (0x02)  /* delta data set ready */