📄 ml675001.s
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/**********************************************************************************/
/* */
/* Copyright (C) 2003 Oki Electric Industry Co., LTD. */
/* */
/* System Name : ML675001 series */
/* Module Name : Common definition include file for ML675001 series */
/* File Name : ML675001.h */
/* Revision : 01.00 */
/* Date : 2003/03/09 */
/* */
/**********************************************************************************/
/*------------------------------ uPLAT-7B core -----------------------------------*/
/*****************************************************/
/* interrupt control register */
/*****************************************************/
.global ICR_BASE.equ ICR_BASE, (0x78000000) /* base address of interrupt control register */
.global IRQ.equ IRQ, (ICR_BASE+0x00) /* IRQ register (R,32,0x00000000) */
.global IRQS.equ IRQS, (ICR_BASE+0x04) /* IRQ soft register (RW,32,0x00000000) */
.global FIQ.equ FIQ, (ICR_BASE+0x08) /* FIQ register (R,32,0x00000000) */
.global FIQRAW.equ FIQRAW, (ICR_BASE+0x0C) /* FIQRAW status register (R,32,--)*/
.global FIQEN.equ FIQEN, (ICR_BASE+0x10) /* FIQ enable register (RW,32,0x00000000)*/
.global IRN.equ IRN, (ICR_BASE+0x14) /* IRQ number register (R,32,0x00000000)*/
.global CIL.equ CIL, (ICR_BASE+0x18) /* current IRQ level register (RW,32,0x00000000)*/
.global ILC0.equ ILC0, (ICR_BASE+0x20) /* IRQ level control register 0 (RW,32,0x00000000) */
.global ILC1.equ ILC1, (ICR_BASE+0x24) /* IRQ level control register 1 (RW,32,0x00000000) */
.global CILCL.equ CILCL, (ICR_BASE+0x28) /* current IRQ level clear register (W,32,--) */
.global CILE.equ CILE, (ICR_BASE+0x2C) /* current IRQ level encode register (R,32,0x00000000) */
/* bit field of IRQ register */
.global IRQ_nIR0.equ IRQ_nIR0, (0x00000001) /* nIR[0] */
.global IRQ_nIR1.equ IRQ_nIR1, (0x00000002) /* nIR[1] */
.global IRQ_nIR2.equ IRQ_nIR2, (0x00000004) /* nIR[2] */
.global IRQ_nIR3.equ IRQ_nIR3, (0x00000008) /* nIR[3] */
.global IRQ_nIR4.equ IRQ_nIR4, (0x00000010) /* nIR[4] */
.global IRQ_nIR5.equ IRQ_nIR5, (0x00000020) /* nIR[5] */
.global IRQ_nIR6.equ IRQ_nIR6, (0x00000040) /* nIR[6] */
.global IRQ_nIR7.equ IRQ_nIR7, (0x00000080) /* nIR[7] */
.global IRQ_nIR8.equ IRQ_nIR8, (0x00000100) /* nIR[8] */
.global IRQ_nIR9.equ IRQ_nIR9, (0x00000200) /* nIR[9] */
.global IRQ_nIR10.equ IRQ_nIR10, (0x00000400) /* nIR[10] */
.global IRQ_nIR11.equ IRQ_nIR11, (0x00000800) /* nIR[11] */
.global IRQ_nIR12.equ IRQ_nIR12, (0x00001000) /* nIR[12] */
.global IRQ_nIR13.equ IRQ_nIR13, (0x00002000) /* nIR[13] */
.global IRQ_nIR14.equ IRQ_nIR14, (0x00004000) /* nIR[14] */
.global IRQ_nIR15.equ IRQ_nIR15, (0x00008000) /* nIR[15] */
/* bit field of IRQS register */
.global IRQS_IRQS.equ IRQS_IRQS, (0x00000002) /* IRQS bit */
/* bit field of FIQ register */
.global FIQ_FIQ.equ FIQ_FIQ, (0x00000001) /* FIQ bit */
/* bit field of FIQRAW register */
.global FIQRAW_FIQRAW.equ FIQRAW_FIQRAW, (0x00000001) /* FIQRAW bit */
/* bit field of FIQEN register */
.global FIQEN_FIQEN.equ FIQEN_FIQEN, (0x00000001) /* FIQEN bit */
/* bit field of IRN register */
.global IRN_IRN.equ IRN_IRN, (0x0000007F) /* IRN[6:0] */
/* bit field of CIL register */
.global CIL_INT_LV1.equ CIL_INT_LV1, (0x00000002) /* interrupt level 1 */
.global CIL_INT_LV2.equ CIL_INT_LV2, (0x00000004) /* interrupt level 2 */
.global CIL_INT_LV3.equ CIL_INT_LV3, (0x00000008) /* interrupt level 3 */
.global CIL_INT_LV4.equ CIL_INT_LV4, (0x00000010) /* interrupt level 4 */
.global CIL_INT_LV5.equ CIL_INT_LV5, (0x00000020) /* interrupt level 5 */
.global CIL_INT_LV6.equ CIL_INT_LV6, (0x00000040) /* interrupt level 6 */
.global CIL_INT_LV7.equ CIL_INT_LV7, (0x00000080) /* interrupt level 7 */
/* bit field of ILC0 register */
.global ILC0_INT_LV1.equ ILC0_INT_LV1, (0x11111111) /* interrupt level 1 */
.global ILC0_INT_LV2.equ ILC0_INT_LV2, (0x22222222) /* interrupt level 2 */
.global ILC0_INT_LV3.equ ILC0_INT_LV3, (0x33333333) /* interrupt level 3 */
.global ILC0_INT_LV4.equ ILC0_INT_LV4, (0x44444444) /* interrupt level 4 */
.global ILC0_INT_LV5.equ ILC0_INT_LV5, (0x55555555) /* interrupt level 5 */
.global ILC0_INT_LV6.equ ILC0_INT_LV6, (0x66666666) /* interrupt level 6 */
.global ILC0_INT_LV7.equ ILC0_INT_LV7, (0x77777777) /* interrupt level 7 */
.global ILC0_ILR0.equ ILC0_ILR0, (0x00000007) /* nIR[0] */
.global ILC0_ILR1.equ ILC0_ILR1, (0x00000070) /* nIR[1],nIR[2],nIR[3] */
.global ILC0_ILR4.equ ILC0_ILR4, (0x00070000) /* nIR[4],nIR[5] */
.global ILC0_ILR6.equ ILC0_ILR6, (0x07000000) /* nIR[6],nIR[7] */
/* bit field of ILC1 register */
.global ILC1_INT_LV1.equ ILC1_INT_LV1, (0x11111111) /* interrupt level 1 */
.global ILC1_INT_LV2.equ ILC1_INT_LV2, (0x22222222) /* interrupt level 2 */
.global ILC1_INT_LV3.equ ILC1_INT_LV3, (0x33333333) /* interrupt level 3 */
.global ILC1_INT_LV4.equ ILC1_INT_LV4, (0x44444444) /* interrupt level 4 */
.global ILC1_INT_LV5.equ ILC1_INT_LV5, (0x55555555) /* interrupt level 5 */
.global ILC1_INT_LV6.equ ILC1_INT_LV6, (0x66666666) /* interrupt level 6 */
.global ILC1_INT_LV7.equ ILC1_INT_LV7, (0x77777777) /* interrupt level 7 */
.global ILC1_ILR8.equ ILC1_ILR8, (0x00000007) /* nIR[8] */
.global ILC1_ILR9.equ ILC1_ILR9, (0x00000070) /* nIR[9] */
.global ILC1_ILR10.equ ILC1_ILR10, (0x00000700) /* nIR[10] */
.global ILC1_ILR11.equ ILC1_ILR11, (0x00007000) /* nIR[11] */
.global ILC1_ILR12.equ ILC1_ILR12, (0x00070000) /* nIR[12] */
.global ILC1_ILR13.equ ILC1_ILR13, (0x00700000) /* nIR[13] */
.global ILC1_ILR14.equ ILC1_ILR14, (0x07000000) /* nIR[14] */
.global ILC1_ILR15.equ ILC1_ILR15, (0x70000000) /* nIR[15] */
/* bit field of CILCL register */
.global CILCL_CLEAR.equ CILCL_CLEAR, (0x00000001) /* most significant '1' bit of CIL is cleared */
/* bit field of CILE register */
.global CILE_CILE.equ CILE_CILE, (0x00000007) /* CILE[2:0] */
/*****************************************************/
/* external memory control register */
/*****************************************************/
.global EMCR_BASE.equ EMCR_BASE, (0x78100000) /* base address */
.global BWC.equ BWC, (EMCR_BASE+0x00) /* bus width control register (RW,32,0x00000008) */
.global ROMAC.equ ROMAC, (EMCR_BASE+0x04) /* external ROM access control register (RW,32,0x00000007) */
.global RAMAC.equ RAMAC, (EMCR_BASE+0x08) /* external SRAM access control register (RW,32,0x00000007) */
.global IO0AC.equ IO0AC, (EMCR_BASE+0x0C) /* external IO0 access control register (RW,32,0x00000007) */
.global IO1AC.equ IO1AC, (EMCR_BASE+0x10) /* external IO1 access control register (RW,32,0x00000007) */
/* bit field of BWC register */
.global BWC_ROMBW0.equ BWC_ROMBW0, (0x00000000) /* ROM disable */
.global BWC_ROMBW16.equ BWC_ROMBW16, (0x00000008) /* ROM 16bit */
.global BWC_RAMBW0.equ BWC_RAMBW0, (0x00000000) /* RAM disable */
.global BWC_RAMBW16.equ BWC_RAMBW16, (0x00000020) /* RAM 16bit */
.global BWC_IO0BW0.equ BWC_IO0BW0, (0x00000000) /* IO0 disable */
.global BWC_IO0BW8.equ BWC_IO0BW8, (0x00000040) /* IO0 8bit */
.global BWC_IO0BW16.equ BWC_IO0BW16, (0x00000080) /* IO0 16 bit */
.global BWC_IO1BW0.equ BWC_IO1BW0, (0x00000000) /* IO1 disable */
.global BWC_IO1BW8.equ BWC_IO1BW8, (0x00000100) /* IO1 8bit */
.global BWC_IO1BW16.equ BWC_IO1BW16, (0x00000200) /* IO1 16bit */
/* bit field of ROMAC register */
.global ROMAC_ROMTYPE.equ ROMAC_ROMTYPE, (0x00000007) /* ROMTYPE[2:0] */
/* bit field of RAMAC register */
.global RAMAC_RAMTYPE.equ RAMAC_RAMTYPE, (0x00000007) /* RAMTYPE[2:0] */
/* bit field of IO0AC register */
.global IO0AC_IO0TYPE.equ IO0AC_IO0TYPE, (0x00000007) /* IO0TYPE[2:0] */
/* bit field of IO1AC register */
.global IO1AC_IO1TYPE.equ IO1AC_IO1TYPE, (0x00000007) /* IO1TYPE[2:0] */
/*****************************************************/
/* system control register */
/*****************************************************/
.global SCR_BASE.equ SCR_BASE, (0xB8000000) /* base address */
.global CLKSTP.equ CLKSTP, (SCR_BASE+0x04) /* clock stop register (W,32,0x00000000) */
.global CGBCNT0.equ CGBCNT0, (SCR_BASE+0x08) /* clock(CGB) control register 0 (RW,32,0x00000000) */
.global CKWT.equ CKWT, (SCR_BASE+0x0C) /* clock wait register (RW,32,0x0000000B) */
.global RMPCON.equ RMPCON, (SCR_BASE+0x10) /* remap control register (RW,32,0x00000000) */
/* bit field of CLKSTP register */
.global CLKSTP_SIO.equ CLKSTP_SIO, (0x00000001) /* SIO HALT */
.global CLKSTP_TIC.equ CLKSTP_TIC, (0x00000002) /* TIC HALT */
.global CLKSTP_HALT.equ CLKSTP_HALT, (0x00000004) /* CPU group HALT */
.global CLKSTP_STBY.equ CLKSTP_STBY, (0x000000F0) /* STANDBY */
/* bit field of CGBCNT0 register */
.global CGBCNT0_HCLK1.equ CGBCNT0_HCLK1, (0x00000000) /* HCLK 1 dividing */
.global CGBCNT0_HCLK2.equ CGBCNT0_HCLK2, (0x00000001) /* HCLK 2 dividing */
.global CGBCNT0_HCLK4.equ CGBCNT0_HCLK4, (0x00000002) /* HCLK 4 dividing */
.global CGBCNT0_HCLK8.equ CGBCNT0_HCLK8, (0x00000003) /* HCLK 8 dividing */
.global CGBCNT0_HCLK16.equ CGBCNT0_HCLK16, (0x00000004) /* HCLK 16 dividing */
.global CGBCNT0_HCLK32.equ CGBCNT0_HCLK32, (0x00000005) /* HCLK 32 dividing */
.global CGBCNT0_CCLK1.equ CGBCNT0_CCLK1, (0x00000000) /* CCLK 1 dividing */
.global CGBCNT0_CCLK2.equ CGBCNT0_CCLK2, (0x00000010) /* CCLK 2 dividing */
.global CGBCNT0_CCLK4.equ CGBCNT0_CCLK4, (0x00000020) /* CCLK 4 dividing */
.global CGBCNT0_CCLK8.equ CGBCNT0_CCLK8, (0x00000030) /* CCLK 8 dividing */
.global CGBCNT0_CCLK16.equ CGBCNT0_CCLK16, (0x00000040) /* CCLK 16 dividing */
.global CGBCNT0_CCLK32.equ CGBCNT0_CCLK32, (0x00000050) /* CCLK 32 dividing */
/* bit field of RMPCON register */
.global RMPCON_ENABLE.equ RMPCON_ENABLE, (0x00000008) /* remap enabled */
.global RMPCON_DISABLE.equ RMPCON_DISABLE, (0x00000000) /* remap disabled */
.global RMPCON_AHB.equ RMPCON_AHB, (0x00000002) /* device space is AHB bus*/
.global RMPCON_EXT.equ RMPCON_EXT, (0x00000000) /* device space is external bus */
.global RMPCON_DRAM.equ RMPCON_DRAM, (0x00000001) /* memory type is DRAM */
.global RMPCON_SRAM.equ RMPCON_SRAM, (0x00000000) /* memory type is SRAM */
.global RMPCON_IRAM.equ RMPCON_IRAM, (0x00000004) /* memory type is internal RAM */
/*****************************************************/
/* system timer control register */
/*****************************************************/
.global STCR_BASE.equ STCR_BASE, (0xB8001000) /* base address */
.global TMEN.equ TMEN, (STCR_BASE+0x04) /* timer enable register (RW,16,0x0000) */
.global TMRLR.equ TMRLR, (STCR_BASE+0x08) /* timer reload register (RW,16,0x0000) */
.global TMOVF.equ TMOVF, (STCR_BASE+0x10) /* overflow register (RW,16,0x0000) */
/* bit field of TMEN register */
.global TMEN_TCEN.equ TMEN_TCEN, (0x0001) /* timer enabled */
/* bit field of TMOVF register */
.global TMOVF_OVF.equ TMOVF_OVF, (0x0001) /* overflow generated */
/*****************************************************/
/* ASIO control register */
/*****************************************************/
.global SC_BASE.equ SC_BASE, (0xB8002000) /* base address */
.global SIOBUF.equ SIOBUF, (SC_BASE+0x00) /* transmiting/receiving buffer register (RW,16,0x0000) */
.global SIOSTA.equ SIOSTA, (SC_BASE+0x04) /* SIO status register (RW,16,0x0000) */
.global SIOCON.equ SIOCON, (SC_BASE+0x08) /* SIO control register (RW,16,0x0000) */
.global SIOBCN.equ SIOBCN, (SC_BASE+0x0C) /* baud rate control register (RW,16,0x0000) */
.global SIOBT.equ SIOBT, (SC_BASE+0x14) /* baud rate timer register (RW,16,0x0000) */
.global SIOTCN.equ SIOTCN, (SC_BASE+0x18) /* SIO test control register (RW,16,0x0000) */
/* bit field of SIOBUF register */
.global SIOBUF_SIOBUF⌨️ 快捷键说明
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