behavioral.h

乘法器的实现

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Xilinxcorelib_mult_gen_v10_0_behavioral_H
#define H_Xilinxcorelib_mult_gen_v10_0_behavioral_H
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


class Xilinxcorelib_mult_gen_v10_0_behavioral: public HSim__s6 {
public:

  char *t632;
  char *t633;
    HSim__s4 PE[22];
    HSim__s1 SE[10];

HSimConstraints *c634;
HSimStringVar C8;
HSimStringVar Cc;
  char t635;
HSim__s4 Ch;
HSim__s4 Cn;
  HSimArrayType T_pipebase;
  HSimArrayType T_pipe;
/* subprogram name get_pipeline_depth */
int F1a(const int C17);
HSim__s4 C2k;
HSim__s4 C2p;
  char *t636;
  char *t637;
  char *t638;
  char *t639;
  int t640;
HSim__s4 C3C;
/* subprogram name get_rounding_const */
char *F3L(HSimConstraints *reConstr, const int C3G, const int C3I);
HSim__s4 C4z;
/* subprogram name check_const_power_two */
char F4N(const char *C4I, const HSimConstraints *constrC4I, const int C4K);
    HSim__s1 SA[10];
  char t641;
    Xilinxcorelib_mult_gen_v10_0_behavioral(const char * name);
    ~Xilinxcorelib_mult_gen_v10_0_behavioral();
    void constructObject();
    void constructPorts();
    void reset();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};

class Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier: public HSim__s6 {
public:
  Xilinxcorelib_mult_gen_v10_0_behavioral *Arch;
    HSim__s1 S6Z;
  char t642;
HSimConstraints *c643;
  char *t644;
HSimConstraints *c645;
  char *t646;
  char t647;
  char t648;
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier(const char* name,
    Xilinxcorelib_mult_gen_v10_0_behavioral *arch,
    HSimConfigDecl* cfg);
    void constructObject();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};

class Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierparmunsigned_multiply: public HSim__s6 {
public:
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *Arch;
HSimConstraints *c649;
  char *t650;
HSimConstraints *c651;
  char *t652;
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierparmunsigned_multiply(const char* name,
    Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *arch,
    HSimConfigDecl* cfg);
    void constructObject();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};

class Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierccm: public HSim__s6 {
public:
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *Arch;
  char *t653;
    HSim__s1 S9N;
HSimConstraints *c654;
  char *t655;
HSimConstraints *c656;
  char *t657;
  char t658;
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierccm(const char* name,
    Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *arch,
    HSimConfigDecl* cfg);
    void constructObject();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};

class Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierccmunsigned_multiply: public HSim__s6 {
public:
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierccm *Arch;
HSimConstraints *c659;
  char *t660;
HSimConstraints *c661;
  char *t662;
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierccmunsigned_multiply(const char* name,
    Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierccm *arch,
    HSimConfigDecl* cfg);
    void constructObject();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};

class Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierpipe2: public HSim__s6 {
public:
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *Arch;
  char *t663;
    HSim__s1 Sd5;
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierpipe2(const char* name,
    Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *arch,
    HSimConfigDecl* cfg);
    void constructObject();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};

class Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierpipex: public HSim__s6 {
public:
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *Arch;
  HSimArrayType T_delaybase;
  HSimArrayType T_delay;
  char *t664;
  char *t665;
    HSim__s1 Ser;
  char *t666;
    HSim__s1 SeD;
  char *t667;
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierpipex(const char* name,
    Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *arch,
    HSimConfigDecl* cfg);
    void constructObject();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};

class Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierhas_zero_detect: public HSim__s6 {
public:
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *Arch;
  char *t668;
HSim__s4 Cg7;
  char t669;
HSimConstraints *c670;
  Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplierhas_zero_detect(const char* name,
    Xilinxcorelib_mult_gen_v10_0_behavioralparallel_multiplier *arch,
    HSimConfigDecl* cfg);
    void constructObject();
    void architectureInstantiate(HSimConfigDecl* cfg);
    virtual void vhdlArchImplement();
};



HSim__s6 *createXilinxcorelib_mult_gen_v10_0_behavioral(const char *name);

#endif