pkg_mult_gen_v10_0.h

乘法器的实现

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Xilinxcorelib_pkg_mult_gen_v10_0_H
#define H_Xilinxcorelib_pkg_mult_gen_v10_0_H

#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


#include "xilinxcorelib.auxlib/pkg_baseblox_v9_1/pkg_baseblox_v9_1.h"
#include "xilinxcorelib.auxlib/prims_utils_v9_1/prims_utils_v9_1.h"
#include "xilinxcorelib.auxlib/prims_constants_v9_1/prims_constants_v9_1.h"
#include "std/textio/textio.h"
#include "ieee/numeric_std/numeric_std.h"
#include "ieee/std_logic_1164/std_logic_1164.h"

class Xilinxcorelib_pkg_mult_gen_v10_0: public HSim__s6 {
public:
HSim__s4 Eh;
HSim__s4 Em;
HSim__s4 Eq;
HSim__s4 Et;
HSim__s4 Ew;
HSim__s4 Ez;
HSim__s4 EC;
HSim__s4 EF;
HSim__s4 EI;
HSim__s4 EL;
HSim__s4 EP;
HSim__s4 ES;
HSim__s4 EV;
HSim__s4 EY;
HSimStringVar E12;
HSim__s4 E19;
HSim__s4 E1c;
HSim__s4 E1f;
HSim__s4 E1i;
HSim__s4 E1m;
HSim__s4 E1q;
HSim__s4 E1s;
HSim__s4 E1v;
HSim__s4 E1y;
HSim__s4 E1B;
HSim__s4 E1E;
HSim__s4 E1I;
HSim__s4 E1K;
HSimStringVar E1P;
HSimStringVar E1W;
HSim__s4 E22;
HSim__s4 E25;
HSim__s4 E28;
HSim__s4 E2c;
HSimStringVar E2f;
HSim__s4 E2n;
HSim__s4 E2r;
HSim__s4 E2u;
HSim__s4 E2x;
HSim__s4 E2A;
  HSimRecordType Port_aspects;
  HSimRecordType Width_rec;
  HSimRecordType Block_mult_rec;
  HSimRecordType One_mult_rec;
  HSimRecordType Two_mult_rec;
/* subprogram name check_generics */
char G4Y(const char E47, const char *E49, const HSimConstraints *constrE49, const char *E4b, const HSimConstraints *constrE4b, const int E4d, const int E4f, const int E4h, const int E4j, const int E4m, const int E4p, const int E4r, const int E4t, const int E4v, const int E4x, const int E4z, const int E4B, const int E4D, const char *E4F, const HSimConstraints *constrE4F, const char *E4H, const HSimConstraints *constrE4H, const int E4J, const int E4L, const int E4N, const int E4Q, const char *E4S, const HSimConstraints *constrE4S, const int E4U);
/* subprogram name modify_family */
char *G54(HSimConstraints *reConstr, const char *E51, const HSimConstraints *constrE51);
/* subprogram name sl_to_int */
int G5b(const char E58);
/* subprogram name mult_gen_log2 */
int G5h(const int E5e);
/* subprogram name mult_gen_log2d */
int G5p(const int E5k);
/* subprogram name calc_fully_pipelined_latency */
int G5L(const char *E5s, const HSimConstraints *constrE5s, const int E5u, const int E5w, const int E5y, const int E5A, const int E5C, const int E5E, const int E5G, const char *E5I, const HSimConstraints *constrE5I);
/* subprogram name calc_fully_pipelined_latency */
int G68(const char E5P, const int E5R, const int E5T, const int E5V, const int E5X, const int E5Z, const int E61, const int E63, const char *E65, const HSimConstraints *constrE65);
/* subprogram name get_true_widths_virtex */
char *G6n(const char E6b, const int E6d, const int E6f, const int E6h, const int E6j);
/* subprogram name get_true_widths */
char *G6F(const char E6r, const int E6t, const int E6v, const int E6x, const int E6z, const char *E6C);
/* subprogram name calc_a_pp */
int G6P(const char E6I, const char *E6L);
/* subprogram name calc_b_pp */
int G6V(const char *E6S);
/* subprogram name hybrid_calc_a_pp */
int G73(const char E6Y, const char *E70);
/* subprogram name hybrid_calc_b_pp */
int G7b(const char E76, const char *E78);
/* subprogram name get_hybrid_configuration */
int G7r(const char E7e, const int E7g, const int E7i, const char *E7k, const char *E7n);
/* subprogram name get_block_mult_cfg */
char *G7H(const char E7u, const int E7w, const int E7y, const char *E7A, const int E7C, const char *E7E);
/* subprogram name get_one_mult_cfg */
char *G80(const char *E7K, const int E7M, const int E7P, const int E7R, const int E7T, const int E7V, const char *E7X);
/* subprogram name get_two_mult_cfg */
char *G8g(const char *E83, const int E85, const int E87, const int E89, const int E8b, const int E8d);
/* subprogram name fab_mult_full_pipe_lat */
int G8q(const int E8j, const int E8m);
/* subprogram name get_emb_mult_max_pipe_stages */
int G8A(const char E8t, const int E8v, const int E8x);
/* subprogram name get_LUT_max_pipe_stages */
int G8M(const char *E8E, const char *E8H, const int E8J);
/* subprogram name get_trimmed_leading_bits */
int G8X(const char *E8Q, const HSimConstraints *constrE8Q, const int E8S, const int E8U);
/* subprogram name get_output_scaling */
int G97(const char *E90, const HSimConstraints *constrE90, const int E92, const int E94);
/* subprogram name check_b_value_all_zeros */
char G9d(const char *E9a, const HSimConstraints *constrE9a);
HSim__s4 E9g;
HSim__s4 E9j;
HSim__s4 E9n;
  char *t127;
HSimStringVar E9x;
HSim__s4 E9A;
HSim__s4 E9G;
/* subprogram name calc_reqd_b_value */
char *G9U(HSimConstraints *reConstr, const char *E9K, const HSimConstraints *constrE9K, const int E9M, const int E9P, const int E9R);
/* subprogram name bitstorep_string */
int Ga2(const char *E9X, const HSimConstraints *constrE9X, const int E9Z);
/* subprogram name calc_shift_bits */
int Gaa(const char *Ea5, const HSimConstraints *constrEa5, const int Ea7);
/* subprogram name get_rom_addr_width */
int Gai(const char Ead, const int Eaf);
/* subprogram name calc_a_input_width */
int Gaw(const int Eam, const int Eap, const int Ear, const int Eat);
/* subprogram name calc_num_pps */
int GaE(const int Eaz, const int EaB);
  HSimRecordType Adder_info_type;
/* subprogram name calc_adder_level */
int Gbq(const int Ebj, const int Ebm);
/* subprogram name calc_last_pp_input_width */
int GbC(const int Ebt, const int Ebv, const int Ebx, const int Ebz);
/* subprogram name calc_pp_width */
int GbZ(const int EbF, const int EbH, const char *EbJ, const HSimConstraints *constrEbJ, const int EbL, const int EbN, const int EbQ, const int EbS, const char EbU, const char EbW);
/* subprogram name calc_last_pp_adder */
int Gcb(const int Ec2, const int Ec4, const int Ec6, const int Ec8);
/* subprogram name calc_last_rom_contents */
char *GcJ(HSimConstraints *reConstr, const int Ece, const int Ecg, const int Eci, const int Eck, const int Ecn, const int Ecq, const int Ecs, const int Ecu, const int Ecw, const char *Ecy, const HSimConstraints *constrEcy, const int EcA, const int EcC, const int EcE, const char EcG);
/* subprogram name calc_rom_contents */
char *Gd4(HSimConstraints *reConstr, const int EcM, const int EcP, const int EcR, const int EcT, const int EcV, const int EcX, const char *EcZ, const HSimConstraints *constrEcZ, const int Ed1);
/* subprogram name calc_rom_start_bit */
int Gdy(const int Ed7, const char *Ed9, const HSimConstraints *constrEd9, const int Edb, const int Edd, const int Edf, const int Edh, const int Edj, const int Edm, const int Edp, const int Edr, const int Edt, const char Edv);
/* subprogram name calc_num_extra_adders */
int GdG(const int EdB, const int EdD);
/* subprogram name get_mem_type */
int Ge3(const char EdJ, const int EdL, const int EdN, const int EdQ, const int EdS, const int EdU, const int EdW, const int EdY, const int Ee0);
/* subprogram name bitsneededtorepresent */
int Gea(const int Ee7);
/* subprogram name bitstorep_bv */
int Gem(const char *Eee, const HSimConstraints *constrEee, const int Eeg, const char Eei);
/* subprogram name int_2_string */
char *Get(HSimConstraints *reConstr, const int Eeq);
/* subprogram name mult_gen_max_of */
int GeB(const int Eew, const int Eey);
/* subprogram name multiply_bv */
char *GeN(HSimConstraints *reConstr, const char *EeE, const HSimConstraints *constrEeE, const char *EeG, const HSimConstraints *constrEeG, const char EeI, const char EeK);
/* subprogram name natural_to_bit_vector */
char *GeW(HSimConstraints *reConstr, const int EeR, const int EeT);
/* subprogram name mult_gen_select_string */
char *Gf6(HSimConstraints *reConstr, const char *EeZ, const HSimConstraints *constrEeZ, const char *Ef1, const HSimConstraints *constrEf1, const char Ef3);
/* subprogram name select_val */
int Gfg(const int Ef9, const int Efb, const char Efd);
/* subprogram name select_val_int */
int Gfs(const int Efj, const int Efm, const int Efp);
/* subprogram name str_to_bv */
char *GfA(HSimConstraints *reConstr, const char *Efv, const HSimConstraints *constrEfv, const int Efx);
/* subprogram name slv_to_str */
char *GfJ(HSimConstraints *reConstr, const char *EfE, const HSimConstraints *constrEfE, const int EfG);
/* subprogram name str_to_slv */
char *GfS(HSimConstraints *reConstr, const char *EfM, const HSimConstraints *constrEfM, const int EfP);
  HSimArrayType Int_array_type;
HSim__s4 EfZ;
HSim__s4 Eg3;
/* subprogram name calc_depth */
int Ggc(const int Eg7, const int Eg9);
/* subprogram name mult_gen_write_meminit_file */
char Ggr(const char *Egf, const HSimConstraints *constrEgf, const int Egi, const int Egk, const char *Egn, const HSimConstraints *constrEgn);

public:
/* subprogram name calc_add_lastpp_delay */
int F1b1(const int C1aU, const int C1aW, const int C1aY);

public:
  Xilinxcorelib_pkg_mult_gen_v10_0(const HSimString &name);
  ~Xilinxcorelib_pkg_mult_gen_v10_0();
};

extern Xilinxcorelib_pkg_mult_gen_v10_0 *XilinxcorelibPkg_mult_gen_v10_0;

#endif