pkg_baseblox_v9_1.h

乘法器的实现

////////////////////////////////////////////////////////////////////////////////
//   ____  ____   
//  /   /\/   /  
// /___/  \  /   
// \   \   \/  
//  \   \        Copyright (c) 2003-2004 Xilinx, Inc.
//  /   /        All Right Reserved. 
// /---/   /\     
// \   \  /  \  
//  \___\/\___\
////////////////////////////////////////////////////////////////////////////////

#ifndef H_Xilinxcorelib_pkg_baseblox_v9_1_H
#define H_Xilinxcorelib_pkg_baseblox_v9_1_H

#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif


#include "xilinxcorelib.auxlib/prims_constants_v9_1/prims_constants_v9_1.h"
#include "ieee/std_logic_1164/std_logic_1164.h"

class Xilinxcorelib_pkg_baseblox_v9_1: public HSim__s6 {
public:
  HSimEnumType T_regtype;
  HSimEnumType T_sync_enable;
  HSimEnumType T_reg_priority;
  HSimEnumType T_bypass_enable;
  HSimEnumType T_add_mode;
  HSimEnumType T_number_format;
  HSimEnumType T_device_family;
/* subprogram name fn_select_sync_enable */
char G1h(const int E1d);
/* subprogram name fn_select_bypass_enable */
char G1p(const int E1k);
/* subprogram name fn_select_sync_priority */
char G1v(const int E1s);
/* subprogram name fn_select_reg_type */
char G1B(const int E1y);
/* subprogram name fn_select_add_mode */
char G1H(const int E1E);
/* subprogram name fn_select_number_format */
char G1N(const int E1K);
/* subprogram name fn_check_family */
char G1V(const char *E1S, const HSimConstraints *constrE1S);
/* subprogram name fn_syncs_in_d_lut */
int G2b(const int E1Y, const int E20, const int E22, const int E24, const int E26, const int E28);
/* subprogram name fn_get_lut_size */
int G2i(const char E2f);
/* subprogram name fn_get_por_value */
char *G2H(HSimConstraints *reConstr, const int E2m, const int E2p, const int E2r, const int E2t, const int E2v, const int E2x, const char *E2A, const HSimConstraints *constrE2A, const char *E2C, const HSimConstraints *constrE2C, const int E2E);

public:

public:
  Xilinxcorelib_pkg_baseblox_v9_1(const HSimString &name);
  ~Xilinxcorelib_pkg_baseblox_v9_1();
};

extern Xilinxcorelib_pkg_baseblox_v9_1 *XilinxcorelibPkg_baseblox_v9_1;

#endif