fir17.tan.summary

来自「采用VHDL语言实现17阶的数字低通滤波器的设计」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.781 ns
From           : x_in[3]
To             : data0[0][11]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 33.125 ns
From           : data0[6][5]
To             : d_out[22]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.424 ns
From           : x_in[8]
To             : data[16][8]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 255.89 MHz ( period = 3.908 ns )
From           : data[6][2]
To             : data0[6][11]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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