fir17.fit.summary

来自「采用VHDL语言实现17阶的数字低通滤波器的设计」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Wed Jul 23 10:00:39 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : fir17
Top-level Entity Name : fir17
Family : Cyclone
Device : EP1C20F400C8
Timing Models : Final
Total logic elements : 2,004 / 20,060 ( 10 % )
Total pins : 36 / 301 ( 12 % )
Total virtual pins : 0
Total memory bits : 0 / 294,912 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )