prev_cmp_fir17.tan.qmsg

采用VHDL语言实现17阶的数字低通滤波器的设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register data\[9\]\[2\] register d_out8\[11\]~reg0 258.93 MHz 3.862 ns Internal " "Info: Clock \"clk\" has Internal fmax of 258.93 MHz between source register \"data\[9\]\[2\]\" and destination register \"d_out8\[11\]~reg0\" (period= 3.862 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.562 ns + Longest register register " "Info: + Longest register to register delay is 3.562 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data\[9\]\[2\] 1 REG LC_X26_Y19_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y19_N1; Fanout = 4; REG Node = 'data\[9\]\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[9][2] } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.594 ns) + CELL(0.575 ns) 2.169 ns d_out8\[2\]~65COUT1 2 COMB LC_X29_Y17_N6 2 " "Info: 2: + IC(1.594 ns) + CELL(0.575 ns) = 2.169 ns; Loc. = LC_X29_Y17_N6; Fanout = 2; COMB Node = 'd_out8\[2\]~65COUT1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.169 ns" { data[9][2] d_out8[2]~65COUT1 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.249 ns d_out8\[3\]~67COUT1 3 COMB LC_X29_Y17_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 2.249 ns; Loc. = LC_X29_Y17_N7; Fanout = 2; COMB Node = 'd_out8\[3\]~67COUT1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { d_out8[2]~65COUT1 d_out8[3]~67COUT1 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.329 ns d_out8\[4\]~69COUT1 4 COMB LC_X29_Y17_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.329 ns; Loc. = LC_X29_Y17_N8; Fanout = 2; COMB Node = 'd_out8\[4\]~69COUT1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { d_out8[3]~67COUT1 d_out8[4]~69COUT1 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.587 ns d_out8\[5\]~71 5 COMB LC_X29_Y17_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 2.587 ns; Loc. = LC_X29_Y17_N9; Fanout = 6; COMB Node = 'd_out8\[5\]~71'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { d_out8[4]~69COUT1 d_out8[5]~71 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.723 ns d_out8\[10\]~81 6 COMB LC_X29_Y16_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 2.723 ns; Loc. = LC_X29_Y16_N4; Fanout = 1; COMB Node = 'd_out8\[10\]~81'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { d_out8[5]~71 d_out8[10]~81 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.562 ns d_out8\[11\]~reg0 7 REG LC_X29_Y16_N5 1 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 3.562 ns; Loc. = LC_X29_Y16_N5; Fanout = 1; REG Node = 'd_out8\[11\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { d_out8[10]~81 d_out8[11]~reg0 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 104 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.968 ns ( 55.25 % ) " "Info: Total cell delay = 1.968 ns ( 55.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.594 ns ( 44.75 % ) " "Info: Total interconnect delay = 1.594 ns ( 44.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.562 ns" { data[9][2] d_out8[2]~65COUT1 d_out8[3]~67COUT1 d_out8[4]~69COUT1 d_out8[5]~71 d_out8[10]~81 d_out8[11]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.562 ns" { data[9][2] {} d_out8[2]~65COUT1 {} d_out8[3]~67COUT1 {} d_out8[4]~69COUT1 {} d_out8[5]~71 {} d_out8[10]~81 {} d_out8[11]~reg0 {} } { 0.000ns 1.594ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.039 ns - Smallest " "Info: - Smallest clock skew is -0.039 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.174 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_K6 295 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K6; Fanout = 295; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.711 ns) 3.174 ns d_out8\[11\]~reg0 2 REG LC_X29_Y16_N5 1 " "Info: 2: + IC(0.994 ns) + CELL(0.711 ns) = 3.174 ns; Loc. = LC_X29_Y16_N5; Fanout = 1; REG Node = 'd_out8\[11\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.705 ns" { clk d_out8[11]~reg0 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 104 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.68 % ) " "Info: Total cell delay = 2.180 ns ( 68.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.994 ns ( 31.32 % ) " "Info: Total interconnect delay = 0.994 ns ( 31.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { clk d_out8[11]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { clk {} clk~out0 {} d_out8[11]~reg0 {} } { 0.000ns 0.000ns 0.994ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.213 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.213 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_K6 295 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K6; Fanout = 295; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.711 ns) 3.213 ns data\[9\]\[2\] 2 REG LC_X26_Y19_N1 4 " "Info: 2: + IC(1.033 ns) + CELL(0.711 ns) = 3.213 ns; Loc. = LC_X26_Y19_N1; Fanout = 4; REG Node = 'data\[9\]\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.744 ns" { clk data[9][2] } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.85 % ) " "Info: Total cell delay = 2.180 ns ( 67.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.033 ns ( 32.15 % ) " "Info: Total interconnect delay = 1.033 ns ( 32.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.213 ns" { clk data[9][2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.213 ns" { clk {} clk~out0 {} data[9][2] {} } { 0.000ns 0.000ns 1.033ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { clk d_out8[11]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { clk {} clk~out0 {} d_out8[11]~reg0 {} } { 0.000ns 0.000ns 0.994ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.213 ns" { clk data[9][2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.213 ns" { clk {} clk~out0 {} data[9][2] {} } { 0.000ns 0.000ns 1.033ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 104 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.562 ns" { data[9][2] d_out8[2]~65COUT1 d_out8[3]~67COUT1 d_out8[4]~69COUT1 d_out8[5]~71 d_out8[10]~81 d_out8[11]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.562 ns" { data[9][2] {} d_out8[2]~65COUT1 {} d_out8[3]~67COUT1 {} d_out8[4]~69COUT1 {} d_out8[5]~71 {} d_out8[10]~81 {} d_out8[11]~reg0 {} } { 0.000ns 1.594ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { clk d_out8[11]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { clk {} clk~out0 {} d_out8[11]~reg0 {} } { 0.000ns 0.000ns 0.994ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.213 ns" { clk data[9][2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.213 ns" { clk {} clk~out0 {} data[9][2] {} } { 0.000ns 0.000ns 1.033ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "d_out0\[11\]~reg0 x_in\[2\] clk 8.348 ns register " "Info: tsu for register \"d_out0\[11\]~reg0\" (data pin = \"x_in\[2\]\", clock pin = \"clk\") is 8.348 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.485 ns + Longest pin register " "Info: + Longest pin to register delay is 11.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns x_in\[2\] 1 PIN PIN_W11 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_W11; Fanout = 4; PIN Node = 'x_in\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { x_in[2] } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.042 ns) + CELL(0.575 ns) 10.092 ns d_out0\[2\]~65COUT1 2 COMB LC_X32_Y19_N6 2 " "Info: 2: + IC(8.042 ns) + CELL(0.575 ns) = 10.092 ns; Loc. = LC_X32_Y19_N6; Fanout = 2; COMB Node = 'd_out0\[2\]~65COUT1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.617 ns" { x_in[2] d_out0[2]~65COUT1 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 10.172 ns d_out0\[3\]~67COUT1 3 COMB LC_X32_Y19_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 10.172 ns; Loc. = LC_X32_Y19_N7; Fanout = 2; COMB Node = 'd_out0\[3\]~67COUT1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { d_out0[2]~65COUT1 d_out0[3]~67COUT1 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 10.252 ns d_out0\[4\]~69COUT1 4 COMB LC_X32_Y19_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 10.252 ns; Loc. = LC_X32_Y19_N8; Fanout = 2; COMB Node = 'd_out0\[4\]~69COUT1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { d_out0[3]~67COUT1 d_out0[4]~69COUT1 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 10.510 ns d_out0\[5\]~71 5 COMB LC_X32_Y19_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 10.510 ns; Loc. = LC_X32_Y19_N9; Fanout = 6; COMB Node = 'd_out0\[5\]~71'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { d_out0[4]~69COUT1 d_out0[5]~71 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 10.646 ns d_out0\[10\]~81 6 COMB LC_X32_Y18_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 10.646 ns; Loc. = LC_X32_Y18_N4; Fanout = 1; COMB Node = 'd_out0\[10\]~81'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { d_out0[5]~71 d_out0[10]~81 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 11.485 ns d_out0\[11\]~reg0 7 REG LC_X32_Y18_N5 1 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 11.485 ns; Loc. = LC_X32_Y18_N5; Fanout = 1; REG Node = 'd_out0\[11\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { d_out0[10]~81 d_out0[11]~reg0 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.443 ns ( 29.98 % ) " "Info: Total cell delay = 3.443 ns ( 29.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.042 ns ( 70.02 % ) " "Info: Total interconnect delay = 8.042 ns ( 70.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.485 ns" { x_in[2] d_out0[2]~65COUT1 d_out0[3]~67COUT1 d_out0[4]~69COUT1 d_out0[5]~71 d_out0[10]~81 d_out0[11]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.485 ns" { x_in[2] {} x_in[2]~out0 {} d_out0[2]~65COUT1 {} d_out0[3]~67COUT1 {} d_out0[4]~69COUT1 {} d_out0[5]~71 {} d_out0[10]~81 {} d_out0[11]~reg0 {} } { 0.000ns 0.000ns 8.042ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.174 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_K6 295 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K6; Fanout = 295; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.711 ns) 3.174 ns d_out0\[11\]~reg0 2 REG LC_X32_Y18_N5 1 " "Info: 2: + IC(0.994 ns) + CELL(0.711 ns) = 3.174 ns; Loc. = LC_X32_Y18_N5; Fanout = 1; REG Node = 'd_out0\[11\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.705 ns" { clk d_out0[11]~reg0 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.68 % ) " "Info: Total cell delay = 2.180 ns ( 68.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.994 ns ( 31.32 % ) " "Info: Total interconnect delay = 0.994 ns ( 31.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { clk d_out0[11]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { clk {} clk~out0 {} d_out0[11]~reg0 {} } { 0.000ns 0.000ns 0.994ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.485 ns" { x_in[2] d_out0[2]~65COUT1 d_out0[3]~67COUT1 d_out0[4]~69COUT1 d_out0[5]~71 d_out0[10]~81 d_out0[11]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.485 ns" { x_in[2] {} x_in[2]~out0 {} d_out0[2]~65COUT1 {} d_out0[3]~67COUT1 {} d_out0[4]~69COUT1 {} d_out0[5]~71 {} d_out0[10]~81 {} d_out0[11]~reg0 {} } { 0.000ns 0.000ns 8.042ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { clk d_out0[11]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { clk {} clk~out0 {} d_out0[11]~reg0 {} } { 0.000ns 0.000ns 0.994ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk d_out0\[0\] d_out0\[0\]~reg0 11.003 ns register " "Info: tco from clock \"clk\" to destination pin \"d_out0\[0\]\" through register \"d_out0\[0\]~reg0\" is 11.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.213 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.213 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_K6 295 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K6; Fanout = 295; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.711 ns) 3.213 ns d_out0\[0\]~reg0 2 REG LC_X32_Y19_N4 1 " "Info: 2: + IC(1.033 ns) + CELL(0.711 ns) = 3.213 ns; Loc. = LC_X32_Y19_N4; Fanout = 1; REG Node = 'd_out0\[0\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.744 ns" { clk d_out0[0]~reg0 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.85 % ) " "Info: Total cell delay = 2.180 ns ( 67.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.033 ns ( 32.15 % ) " "Info: Total interconnect delay = 1.033 ns ( 32.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.213 ns" { clk d_out0[0]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.213 ns" { clk {} clk~out0 {} d_out0[0]~reg0 {} } { 0.000ns 0.000ns 1.033ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.566 ns + Longest register pin " "Info: + Longest register to pin delay is 7.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d_out0\[0\]~reg0 1 REG LC_X32_Y19_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y19_N4; Fanout = 1; REG Node = 'd_out0\[0\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { d_out0[0]~reg0 } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.442 ns) + CELL(2.124 ns) 7.566 ns d_out0\[0\] 2 PIN PIN_N4 0 " "Info: 2: + IC(5.442 ns) + CELL(2.124 ns) = 7.566 ns; Loc. = PIN_N4; Fanout = 0; PIN Node = 'd_out0\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.566 ns" { d_out0[0]~reg0 d_out0[0] } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 28.07 % ) " "Info: Total cell delay = 2.124 ns ( 28.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.442 ns ( 71.93 % ) " "Info: Total interconnect delay = 5.442 ns ( 71.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.566 ns" { d_out0[0]~reg0 d_out0[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.566 ns" { d_out0[0]~reg0 {} d_out0[0] {} } { 0.000ns 5.442ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.213 ns" { clk d_out0[0]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.213 ns" { clk {} clk~out0 {} d_out0[0]~reg0 {} } { 0.000ns 0.000ns 1.033ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.566 ns" { d_out0[0]~reg0 d_out0[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.566 ns" { d_out0[0]~reg0 {} d_out0[0] {} } { 0.000ns 5.442ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "data\[16\]\[9\] x_in\[9\] clk -4.798 ns register " "Info: th for register \"data\[16\]\[9\]\" (data pin = \"x_in\[9\]\", clock pin = \"clk\") is -4.798 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.174 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_K6 295 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K6; Fanout = 295; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.711 ns) 3.174 ns data\[16\]\[9\] 2 REG LC_X31_Y16_N1 4 " "Info: 2: + IC(0.994 ns) + CELL(0.711 ns) = 3.174 ns; Loc. = LC_X31_Y16_N1; Fanout = 4; REG Node = 'data\[16\]\[9\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.705 ns" { clk data[16][9] } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.68 % ) " "Info: Total cell delay = 2.180 ns ( 68.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.994 ns ( 31.32 % ) " "Info: Total interconnect delay = 0.994 ns ( 31.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { clk data[16][9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { clk {} clk~out0 {} data[16][9] {} } { 0.000ns 0.000ns 0.994ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.987 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns x_in\[9\] 1 PIN PIN_U10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_U10; Fanout = 4; PIN Node = 'x_in\[9\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { x_in[9] } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.397 ns) + CELL(0.115 ns) 7.987 ns data\[16\]\[9\] 2 REG LC_X31_Y16_N1 4 " "Info: 2: + IC(6.397 ns) + CELL(0.115 ns) = 7.987 ns; Loc. = LC_X31_Y16_N1; Fanout = 4; REG Node = 'data\[16\]\[9\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.512 ns" { x_in[9] data[16][9] } "NODE_NAME" } } { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 19.91 % ) " "Info: Total cell delay = 1.590 ns ( 19.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.397 ns ( 80.09 % ) " "Info: Total interconnect delay = 6.397 ns ( 80.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.987 ns" { x_in[9] data[16][9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.987 ns" { x_in[9] {} x_in[9]~out0 {} data[16][9] {} } { 0.000ns 0.000ns 6.397ns } { 0.000ns 1.475ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.174 ns" { clk data[16][9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.174 ns" { clk {} clk~out0 {} data[16][9] {} } { 0.000ns 0.000ns 0.994ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.987 ns" { x_in[9] data[16][9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.987 ns" { x_in[9] {} x_in[9]~out0 {} data[16][9] {} } { 0.000ns 0.000ns 6.397ns } { 0.000ns 1.475ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}