prev_cmp_fir17.qmsg

采用VHDL语言实现17阶的数字低通滤波器的设计

{ "Info" "ISGN_START_ELABORATION_TOP" "fir17 " "Info: Elaborating entity \"fir17\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[16\]\[11\] data\[16\]\[10\] " "Info: Duplicate register \"data\[16\]\[11\]\" merged to single register \"data\[16\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 37 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[15\]\[11\] data\[15\]\[10\] " "Info: Duplicate register \"data\[15\]\[11\]\" merged to single register \"data\[15\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[14\]\[11\] data\[14\]\[10\] " "Info: Duplicate register \"data\[14\]\[11\]\" merged to single register \"data\[14\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[13\]\[11\] data\[13\]\[10\] " "Info: Duplicate register \"data\[13\]\[11\]\" merged to single register \"data\[13\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[12\]\[11\] data\[12\]\[10\] " "Info: Duplicate register \"data\[12\]\[11\]\" merged to single register \"data\[12\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[11\]\[11\] data\[11\]\[10\] " "Info: Duplicate register \"data\[11\]\[11\]\" merged to single register \"data\[11\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[10\]\[11\] data\[10\]\[10\] " "Info: Duplicate register \"data\[10\]\[11\]\" merged to single register \"data\[10\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[9\]\[11\] data\[9\]\[10\] " "Info: Duplicate register \"data\[9\]\[11\]\" merged to single register \"data\[9\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[8\]\[11\] data\[8\]\[10\] " "Info: Duplicate register \"data\[8\]\[11\]\" merged to single register \"data\[8\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[7\]\[11\] data\[7\]\[10\] " "Info: Duplicate register \"data\[7\]\[11\]\" merged to single register \"data\[7\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[6\]\[11\] data\[6\]\[10\] " "Info: Duplicate register \"data\[6\]\[11\]\" merged to single register \"data\[6\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[5\]\[11\] data\[5\]\[10\] " "Info: Duplicate register \"data\[5\]\[11\]\" merged to single register \"data\[5\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[4\]\[11\] data\[4\]\[10\] " "Info: Duplicate register \"data\[4\]\[11\]\" merged to single register \"data\[4\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[3\]\[11\] data\[3\]\[10\] " "Info: Duplicate register \"data\[3\]\[11\]\" merged to single register \"data\[3\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[2\]\[11\] data\[2\]\[10\] " "Info: Duplicate register \"data\[2\]\[11\]\" merged to single register \"data\[2\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[1\]\[11\] data\[1\]\[10\] " "Info: Duplicate register \"data\[1\]\[11\]\" merged to single register \"data\[1\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[0\]\[11\] data\[0\]\[10\] " "Info: Duplicate register \"data\[0\]\[11\]\" merged to single register \"data\[0\]\[10\]\"" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 48 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "415 " "Info: Implemented 415 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "108 " "Info: Implemented 108 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "295 " "Info: Implemented 295 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Allocated 156 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 22 01:04:59 2008 " "Info: Processing ended: Tue Jul 22 01:04:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}