prev_cmp_fir17.qmsg

采用VHDL语言实现17阶的数字低通滤波器的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 22 01:04:57 2008 " "Info: Processing started: Tue Jul 22 01:04:57 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fir17 -c fir17 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fir17 -c fir17" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fir17.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fir17.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fir17-flex " "Info: Found design unit 1: fir17-flex" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 23 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fir17 " "Info: Found entity 1: fir17" {  } { { "fir17.vhd" "" { Text "D:/altera/lianxi/pfir/fir17/fir17.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}