fir17.vhd

采用VHDL语言实现17阶的数字低通滤波器的设计

LIBRARY lpm;                   -- Using chang fa qi 
USE lpm.lpm_components.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY fir17 IS                      ------> Interface
  PORT ( 
         clk    : IN STD_LOGIC;
         x_in   : IN  STD_LOGIC_VECTOR(10 DOWNTO 0);
         d_out  : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
       );
END fir17;

ARCHITECTURE flex OF fir17 IS
  SUBTYPE N1BIT IS STD_LOGIC_VECTOR(11 DOWNTO 0);
  SUBTYPE N2BIT IS STD_LOGIC_VECTOR(23 DOWNTO 0);
  TYPE ARRAY_N1BITF IS ARRAY (16 downto 0 ) OF N1BIT;--  the lenth of fir
  TYPE ARRAY_N2BITF IS ARRAY (8 downto 0 ) OF N1BIT;--  the lenth of fir
  TYPE ARRAY_N22BITF IS ARRAY (8 downto 0 ) OF N2BIT;--  the lenth of fir
  SIGNAL  datareg     :  N2BIT;
  SIGNAL  data:  ARRAY_N1BITF; 
  SIGNAL  data0:  ARRAY_N2BITF; 
  SIGNAL  data1:  ARRAY_N2BITF; -- Coefficient array 
  SIGNAL  data2:  ARRAY_N22BITF; 
                                       
BEGIN
datamv: PROCESS (clk)  -- shu ju yi wei
  BEGIN
    if clk'event and clk='1' then 
    if x_in(10)='1' then
    data(16)<='1'&x_in;
    else
    data(16)<='0'&x_in;
    end if;
    end if;
  END PROCESS;
MulGen2: FOR I IN 0 TO 15 GENERATE 
         PROCESS (clk)  -- shu ju yi wei
           BEGIN
           if clk'event and clk='1' then 
           data(i)<=data(i+1);
           end if;
           END PROCESS;
END GENERATE;

 MulGen0: FOR I IN 8 downTO 1 GENERATE 
 PROCESS(clk)   ------ dui cheng xiang xiang jia
  BEGIN
   if clk'event and clk='1' then 
   data0(i)<=data(i)+data(17-i);
   end if;
  END PROCESS ;
END GENERATE;
PROCESS(clk)  ------ dui cheng xiang xiang jia 
  BEGIN
   if clk'event and clk='1' then 
   data0(0)<=data(0)+x_in;
   end if;
END PROCESS ;

PROCESS(clk)-- fir xi shu  
constant dff0:std_logic_vector(11 downto 0):= conv_std_logic_vector(45,12);
constant dff1:std_logic_vector(11 downto 0):= conv_std_logic_vector(46,12);
constant dff2:std_logic_vector(11 downto 0):= conv_std_logic_vector(47,12);
constant dff3:std_logic_vector(11 downto 0):= conv_std_logic_vector(48,12);
constant dff4:std_logic_vector(11 downto 0):= conv_std_logic_vector(49,12);
constant dff5:std_logic_vector(11 downto 0):= conv_std_logic_vector(50,12);
constant dff6:std_logic_vector(11 downto 0):= conv_std_logic_vector(51,12);
constant dff7:std_logic_vector(11 downto 0):= conv_std_logic_vector(51,12);
constant dff8:std_logic_vector(11 downto 0):= conv_std_logic_vector(51,12);
  BEGIN
   if clk'event and clk='1' then 
   data1(0)<=dff0;
   data1(1)<=dff1;
   data1(2)<=dff2;
   data1(3)<=dff3;
   data1(4)<=dff4;
   data1(5)<=dff5;
   data1(6)<=dff6;
   data1(7)<=dff7;
   data1(8)<=dff8;
   end if;
END PROCESS ;
  MulGen1: FOR I IN 0 TO 8 GENERATE 
  FIR: lpm_mult             -- Multiply p(i) = f(i) * x(i);
              GENERIC MAP ( LPM_WIDTHA => 12, LPM_WIDTHB => 12, 
                      LPM_REPRESENTATION => "SIGNED", 
                      LPM_WIDTHP => 24, 
                      LPM_WIDTHS => 1)  
        PORT MAP ( dataa => data0(I), 
                   datab => data1(I),
                   result =>data2(I));
  END GENERATE; 
datareg<=(((data2(0)+data2(1))+(data2(2)+data2(3)))+((data2(4)+data2(5))+(data2(6)+data2(7))))+data2(8);
d_out<=datareg;
END flex;