8bit_led_scan.txt

8位七段码动态扫描控制VHDL设计。动态扫描模块

library ieee;
use ieee.std_logic_1164.all;

entity ctr_led7 is
  port( clk, wr, clr: in std_logic;
		data: in std_logic_vector(31 downto 0);
		dig: out std_logic_vector(7 downto 0);
		seg: out std_logic_vector(7 downto 0));
end ctr_led7;

architecture ex1 of ctr_led7 is
  type d_buffer is array (0 to 7) of std_logic_vector(3 downto 0);
  shared variable ram: d_buffer;--:= ("0000","0001","0010","0011","0100","0101","0110","0111");
  
  type state is (s0,s1,s2,s3,s4,s5,s6,s7);
  signal p_state, n_state: state;
  
  signal bcd: std_logic_vector(3 downto 0);
begin
------led7 decoder--------------------------
  seg <="00111111" when bcd="0000" else
		"00000110" when bcd="0001" else
       	"01011011" when bcd="0010" else
       	"01001111" when bcd="0011" else
       	"01100110" when bcd="0100" else
       	"01101101" when bcd="0101" else
       	"01111101" when bcd="0110" else
       	"00000111" when bcd="0111" else
       	"01111111" when bcd="1000" else
       	"01101111" when bcd="1001" else
       	"00000000" ;
-------write data into d_buffer--------------
p0:process(clr,wr) is
begin
  if clr='0' then
    ram(0):="0000";
    ram(1):="0000";
    ram(2):="0000";
    ram(3):="0000"; 
    ram(4):="0000";
    ram(5):="0000";
    ram(6):="0000";
    ram(7):="0000";                       
  elsif rising_edge(wr) then
    ram(0):=data(3 downto 0);
    ram(1):=data(7 downto 4);
    ram(2):=data(11 downto 8);
    ram(3):=data(15 downto 12); 
    ram(4):=data(19 downto 16);
    ram(5):=data(23 downto 20);
    ram(6):=data(27 downto 24);
    ram(7):=data(31 downto 28);       
  end if;
end process p0;      
-------dynamic scan using state machine------
seq: process (clk) is
begin
  if (rising_edge (clk)) then
      p_state <= n_state;
  end if;
end process seq;

com: process (p_state) is
begin
  case p_state is
    when s0=>
      dig<="11111110";
      bcd<=ram(0);
      n_state <= s1;   
    when s1=>
      dig<="11111101";
      bcd<=ram(1);
      n_state <= s2; 
    when s2=>
      dig<="11111011";
      bcd<=ram(2);
      n_state <= s3; 
    when s3=>
      dig<="11110111";
      bcd<=ram(3);
      n_state <= s4;
    when s4=>
      dig<="11101111";
      bcd<=ram(4);
      n_state <= s5; 
    when s5=>
      dig<="11011111";
      bcd<=ram(5);
      n_state <= s6; 
    when s6=>
      dig<="10111111";
      bcd<=ram(6);
      n_state <= s7; 
    when s7=>
      dig<="01111111";
      bcd<=ram(7);
      n_state <= s0;                    
  end case; 
end process com;
---------------------------------
end ex1;