71x_init_c.s

基于微芯力公司的STR71x开发平台的ARM7

;71x_init_c.s : 使用C运行库的初始化程序
;此文件由STMicroelectronics的71x_init.s修改而来
;*******************************************************************************
;* Modified by Wen, for project using C lib without scaf file 
;* History: (ST)
;*  13/01/2006 : V3.1
;*  24/05/2005 : V3.0
;*  30/11/2004 : V2.0
;*  14/07/2004 : V1.3
;*  01/01/2004 : V1.2
;*******************************************************************************

        PRESERVE8
        AREA    Init, CODE, READONLY

; ---ARM状态寄存器PSR中模式位和中断禁止位定义

Mode_USR            EQU    0x10
Mode_FIQ            EQU    0x11
Mode_IRQ            EQU    0x12
Mode_SVC            EQU    0x13
Mode_ABT            EQU    0x17
Mode_UNDEF          EQU    0x1B
Mode_SYS            EQU    0x1F ; available on ARM Arch 4 and later

I_Bit               EQU    0x80 ; when I bit is set, IRQ is disabled
F_Bit               EQU    0x40 ; when F bit is set, FIQ is disabled


; --- 系统存储器起始地址

RAM_Base            EQU    0x20000000	;片内存储器
RAM_Limit           EQU    0x20010000
SRAM_Limit          EQU    0x62080000	;外部存储器
SRAM_Base           EQU    0x60000000
Stack_Base          EQU    RAM_Limit

; --- 各个模式下堆栈大小
USR_Stack_Length    EQU    1024
IRQ_Stack_Length    EQU    1024
SVC_Stack_Length    EQU    256
FIQ_Stack_Length    EQU    64
ABT_Stack_Length    EQU    64
UNDEF_Stack_Length  EQU    64

USR_Stack           EQU    Stack_Base                 ; USR stack
IRQ_Stack           EQU    USR_Stack-USR_Stack_Length ; followed by IRQ stack
SVC_Stack           EQU    IRQ_Stack-IRQ_Stack_Length ; followed by SVC stack
FIQ_Stack           EQU    SVC_Stack-SVC_Stack_Length ; followed by FIQ stack
ABT_Stack           EQU    FIQ_Stack-FIQ_Stack_Length ; followed by ABT stack
UNDEF_Stack         EQU    ABT_Stack-ABT_Stack_Length ; followed by UNDEF stack

; --- 定义STR710中断控制器控制寄存器地址
EIC_Base_addr       EQU    0xFFFFF800; EIC base address
ICR_off_addr        EQU    0x00      ; Interrupt Control register offset
CIPR_off_addr       EQU    0x08      ; Current Interrupt Priority Register offset
IVR_off_addr        EQU    0x18      ; Interrupt Vector Register offset
FIR_off_addr        EQU    0x1C      ; Fast Interrupt Register offset
IER_off_addr        EQU    0x20      ; Interrupt Enable Register offset
IPR_off_addr        EQU    0x40      ; Interrupt Pending Bit Register offset
SIR0_off_addr       EQU    0x60      ; Source Interrupt Register 0

; --- 定义STR710外部存储接口控制器寄存器地址
EMI_BCON0   EQU    0x6C000000
EMI_BCON1   EQU    0x6C000004
EMI_BCON2   EQU    0x6C000008
EMI_BCON3   EQU    0x6C00000C

; --- 定义STR710时钟控制器寄存器地址
RCCU_CCR       EQU    0xA0000000                      
RCCU_CFR       EQU    0xA0000008
RCCU_PLL1CR    EQU    0xA0000018
RCCU_PER       EQU    0xA000001C
RCCU_SMR       EQU    0xA0000020
PCU_MDIVR      EQU    0xA0000040
PCU_PDIVR      EQU    0xA0000044
PCU_RSTR       EQU    0xA0000048
PCU_PLL2CR     EQU    0xA000004C
PCU_BOOTCR     EQU    0xA0000050
PCU_PWRCR      EQU    0xA0000054

; --- 定义STR710 P2端口控制寄存器地址
GPIO2_Base_addr     EQU    0xE0005000; GPIO2 base address
PC0_off_addr        EQU    0x00      ; Port Configuration Register 0 offset
PC1_off_addr        EQU    0x04      ; Port Configuration Register 1 offset
PC2_off_addr        EQU    0x08      ; Port Configuration Register 2 offset
PD_off_addr         EQU    0x0C      ; Port Data Register offset

; --- 定义STR710 启动地址映射控制寄存器地址
CPM_Base_addr       EQU    0xA0000040; CPM Base Address
BOOTCR_off_addr     EQU    0x10      ; CPM - Boot Configuration Register
FLASH_mask          EQU    0x0000    ; to remap FLASH at 0x0
RAM_mask            EQU    0x0002    ; to remap RAM at 0x0
EXTMEM_mask         EQU    0x0003    ; to remap EXTMEM at 0x0

; --- 定义STR710 内部外设总线控制寄存器地址
APB1_base_addr      EQU    0xC0000000          ; APB Bridge1 Base Address
APB2_base_addr      EQU    0xE0000000          ; APB Bridge2 Base Address
CKDIS_off_addr      EQU    0x10                ; APB Bridge1 - Clock Disable  Register
SWRES_off_addr      EQU    0x14                ; APB Bridge1 - Software Reset Register
CKDIS1_config_all   EQU    0x27FB              ; To enable/disable clock of all APB1's peripherals
SWRES1_config_all   EQU    0x27FB              ; To reset all APB1's peripherals
CKDIS2_config_all   EQU    0x7FDD              ; To enable/disable clock of all APB2's peripherals
SWRES2_config_all   EQU    0x7FDD              ; To reset all APB2's peripherals

;*******************************************************************************
;*******                         -- 宏定义 --                            *******
;*******************************************************************************
;****************************************************************************          
;* Macro Name     : SYSCLK_INIT ，用于设定系统时钟和锁相环的宏
;* Description    : This macro Initialise PLL1, MCLK, PCLK1, PCLK2.
;* Input          : None.
;* Output         : None.
;* CLK=16Mhz -> CLK2=CLK/2=8Mhz -> CLK3=PLL1 out=48Mhz -> RCLK=CLK3=48Mhz -> *
;* -> MCLK=RCLK=48Mhz; PCLK1=RCLK/2=24Mhz; PCLK2=RCLK/4=12Mhz               *
;* PLL1 out = CLK2 * 12 / 2 ;  PLL2被关闭;  USBCLK的输入直接作为USB模块时钟 *
;****************************************************************************

        MACRO   
        SYSCLK_INIT
	 
        LDR     R0,=0x0051                 
        LDR     R1,=RCCU_PLL1CR
        STR     R0,[R1]            ;设置PLL1
        
        LDR     R0,=0x0000                 
        LDR     R1,=RCCU_CCR
        STR     R0,[R1]                   
        LDR     R0,=0x8009                 
        LDR     R1,=RCCU_CFR
        STR     R0,[R1]            ;选择PLL1输出作为时钟源
         
        LDR     R0,=0x0000                
        LDR     R1,=PCU_MDIVR
        STR     R0,[R1]            ;MCLK=RCLK
        
        LDR     R0,=0x0201                
        LDR     R1,=PCU_PDIVR
        STR     R0,[R1]            ;PCLK1=RCLK/2;PCLK2=RCLK/4
          
        LDR     R0,=0x0007                 
        LDR     R1,=PCU_PLL2CR
        STR     R0,[R1]            ;设置USB模块时钟源,关闭PLL2
        MEND

;*******************************************************************************
;* Macro Name     : EMI_INIT  用于设定外总线引脚功能和4组总线参数的宏
;* Description    : This macro Initialize EMI bank 0-3
;* Input          : None.
;* Output         : None.
;*******************************************************************************
        MACRO   
        EMI_INIT
        LDR     r0, =GPIO2_Base_addr      ; Configure P2.0 -> 3 in AF_PP mode
        LDR     r2, [r0, #PC0_off_addr]
        ORR     r2, r2,#0x0000000F
        STR     r2, [r0, #PC0_off_addr]
        LDR     r2, [r0, #PC1_off_addr]
        ORR     r2, r2,#0x0000000F
        STR     r2, [r0, #PC1_off_addr]
        LDR     r2, [r0, #PC2_off_addr]
        ORR     r2, r2,#0x0000000F
        STR     r2, [r0, #PC2_off_addr]
;wen******************************************************************
;配置STR710F的EMI接口
;CS0->16位高速NOR FLASH，CS1->16位高速SRAM
;CS2->16位以太网控制器， CS3->CPLD IO器件
        LDR     R0,=0x800d         ;打开BANK0,设定位宽为16位，3等待周期
        LDR     R1,=EMI_BCON0
        STR     R0,[R1]
        
        LDR     R0,=0x8009         ;打开BANK1,设定位宽为16位，2等待周期
        LDR     R1,=EMI_BCON1
        STR     R0,[R1]
        
        LDR     R0,=0x8029         ;打开BANK2,设定位宽为16位，10等待周期
        LDR     R1,=EMI_BCON2
        STR     R0,[R1]
        
        LDR     R0,=0x800d         ;打开BANK3,设定位宽为16位，3等待周期
        LDR     R1,=EMI_BCON3
        STR     R0,[R1]