📄 convolutional_inside.mdl
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SuppressErrorStatus off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Inport
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
SampleTime "-1"
}
Block {
BlockType Memory
X0 "0"
InheritSampleTime off
LinearizeMemory off
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
}
Block {
BlockType Outport
Port "1"
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "convolutional_inside"
Location [237, 120, 1157, 606]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Inport
Name "In1"
Position [60, 238, 90, 252]
DropShadow on
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Logic
Name "Logical\nOperator1"
Ports [7, 1]
Position [545, 93, 575, 197]
DropShadow on
Operator "XOR"
Inputs "7"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical\nOperator2"
Ports [5, 1]
Position [545, 296, 580, 384]
DropShadow on
Operator "XOR"
Inputs "5"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Memory
Name "Memory"
Position [130, 230, 160, 260]
DropShadow on
}
Block {
BlockType Memory
Name "Memory1"
Position [185, 230, 215, 260]
DropShadow on
}
Block {
BlockType Memory
Name "Memory2"
Position [235, 230, 265, 260]
DropShadow on
}
Block {
BlockType Memory
Name "Memory3"
Position [285, 230, 315, 260]
DropShadow on
}
Block {
BlockType Memory
Name "Memory4"
Position [335, 230, 365, 260]
DropShadow on
}
Block {
BlockType Memory
Name "Memory5"
Position [385, 230, 415, 260]
DropShadow on
}
Block {
BlockType Memory
Name "Memory6"
Position [435, 230, 465, 260]
DropShadow on
}
Block {
BlockType Memory
Name "Memory7"
Position [485, 230, 515, 260]
DropShadow on
InheritSampleTime on
}
Block {
BlockType Outport
Name "Out1"
Position [760, 138, 790, 152]
DropShadow on
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "Out2"
Position [765, 333, 795, 347]
DropShadow on
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Memory"
SrcPort 1
Points [0, 0; 5, 0]
Branch {
DstBlock "Memory1"
DstPort 1
}
Branch {
Points [0, -130]
DstBlock "Logical\nOperator1"
DstPort 2
}
}
Line {
SrcBlock "Memory1"
SrcPort 1
Points [0, 0]
Branch {
Points [0, -115]
DstBlock "Logical\nOperator1"
DstPort 3
}
Branch {
Points [0, 0]
Branch {
DstBlock "Memory2"
DstPort 1
}
Branch {
Points [0, 80]
DstBlock "Logical\nOperator2"
DstPort 2
}
}
}
Line {
SrcBlock "Memory2"
SrcPort 1
Points [0, 0]
Branch {
Points [5, 0; 0, -100]
DstBlock "Logical\nOperator1"
DstPort 4
}
Branch {
Points [0, 0]
Branch {
DstBlock "Memory3"
DstPort 1
}
Branch {
Points [5, 0; 0, 95]
DstBlock "Logical\nOperator2"
DstPort 3
}
}
}
Line {
SrcBlock "Memory3"
SrcPort 1
Points [0, 0]
Branch {
DstBlock "Memory4"
DstPort 1
}
Branch {
Points [5, 0; 0, 110]
DstBlock "Logical\nOperator2"
DstPort 4
}
}
Line {
SrcBlock "Memory4"
SrcPort 1
Points [0, 0]
Branch {
DstBlock "Memory5"
DstPort 1
}
Branch {
Points [0, -85]
DstBlock "Logical\nOperator1"
DstPort 5
}
}
Line {
SrcBlock "Memory5"
SrcPort 1
DstBlock "Memory6"
DstPort 1
}
Line {
SrcBlock "Memory6"
SrcPort 1
Points [0, 0]
Branch {
DstBlock "Memory7"
DstPort 1
}
Branch {
Points [0, -70]
DstBlock "Logical\nOperator1"
DstPort 6
}
}
Line {
SrcBlock "Logical\nOperator1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator2"
SrcPort 1
DstBlock "Out2"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
DstBlock "Memory"
DstPort 1
}
Branch {
Points [0, 65]
DstBlock "Logical\nOperator2"
DstPort 1
}
Branch {
Points [0, -145]
DstBlock "Logical\nOperator1"
DstPort 1
}
}
Line {
SrcBlock "Memory7"
SrcPort 1
Points [0, 0; 5, 0]
Branch {
Points [0, -55]
DstBlock "Logical\nOperator1"
DstPort 7
}
Branch {
Points [0, 125]
DstBlock "Logical\nOperator2"
DstPort 5
}
}
}
}
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