stopwatch.tan.qmsg

利用Quarteus II 6.0 设计一个秒表

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "cnt8\[0\] sg\[0\]\$latch clk_led 9.368 ns " "Info: Found hold time violation between source  pin or register \"cnt8\[0\]\" and destination pin or register \"sg\[0\]\$latch\" for clock \"clk_led\" (Hold time is 9.368 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "12.264 ns + Largest " "Info: + Largest clock skew is 12.264 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_led destination 19.737 ns + Longest register " "Info: + Longest clock path from clock \"clk_led\" to destination register is 19.737 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk_led 1 CLK PIN_122 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 3; CLK Node = 'clk_led'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_led } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(0.935 ns) 7.697 ns cnt8\[2\] 2 REG LC_X12_Y11_N9 19 " "Info: 2: + IC(5.287 ns) + CELL(0.935 ns) = 7.697 ns; Loc. = LC_X12_Y11_N9; Fanout = 19; REG Node = 'cnt8\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.222 ns" { clk_led cnt8[2] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(0.114 ns) 9.660 ns Mux10~204 3 COMB LC_X15_Y10_N5 1 " "Info: 3: + IC(1.849 ns) + CELL(0.114 ns) = 9.660 ns; Loc. = LC_X15_Y10_N5; Fanout = 1; COMB Node = 'Mux10~204'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.963 ns" { cnt8[2] Mux10~204 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.651 ns) + CELL(0.590 ns) 11.901 ns Mux10~205 4 COMB LC_X12_Y11_N3 1 " "Info: 4: + IC(1.651 ns) + CELL(0.590 ns) = 11.901 ns; Loc. = LC_X12_Y11_N3; Fanout = 1; COMB Node = 'Mux10~205'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.241 ns" { Mux10~204 Mux10~205 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.114 ns) 12.783 ns Mux10~206 5 COMB LC_X11_Y11_N8 1 " "Info: 5: + IC(0.768 ns) + CELL(0.114 ns) = 12.783 ns; Loc. = LC_X11_Y11_N8; Fanout = 1; COMB Node = 'Mux10~206'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.882 ns" { Mux10~205 Mux10~206 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 13.079 ns Mux10~208 6 COMB LC_X11_Y11_N9 8 " "Info: 6: + IC(0.182 ns) + CELL(0.114 ns) = 13.079 ns; Loc. = LC_X11_Y11_N9; Fanout = 8; COMB Node = 'Mux10~208'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { Mux10~206 Mux10~208 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.442 ns) 14.742 ns Mux19~27 7 COMB LC_X12_Y9_N6 7 " "Info: 7: + IC(1.221 ns) + CELL(0.442 ns) = 14.742 ns; Loc. = LC_X12_Y9_N6; Fanout = 7; COMB Node = 'Mux19~27'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.663 ns" { Mux10~208 Mux19~27 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.881 ns) + CELL(0.114 ns) 19.737 ns sg\[0\]\$latch 8 REG LC_X12_Y11_N0 1 " "Info: 8: + IC(4.881 ns) + CELL(0.114 ns) = 19.737 ns; Loc. = LC_X12_Y11_N0; Fanout = 1; REG Node = 'sg\[0\]\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.995 ns" { Mux19~27 sg[0]$latch } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.898 ns ( 19.75 % ) " "Info: Total cell delay = 3.898 ns ( 19.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.839 ns ( 80.25 % ) " "Info: Total interconnect delay = 15.839 ns ( 80.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.737 ns" { clk_led cnt8[2] Mux10~204 Mux10~205 Mux10~206 Mux10~208 Mux19~27 sg[0]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.737 ns" { clk_led clk_led~out0 cnt8[2] Mux10~204 Mux10~205 Mux10~206 Mux10~208 Mux19~27 sg[0]$latch } { 0.000ns 0.000ns 5.287ns 1.849ns 1.651ns 0.768ns 0.182ns 1.221ns 4.881ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.590ns 0.114ns 0.114ns 0.442ns 0.114ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_led source 7.473 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_led\" to source register is 7.473 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk_led 1 CLK PIN_122 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 3; CLK Node = 'clk_led'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_led } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(0.711 ns) 7.473 ns cnt8\[0\] 2 REG LC_X12_Y11_N6 18 " "Info: 2: + IC(5.287 ns) + CELL(0.711 ns) = 7.473 ns; Loc. = LC_X12_Y11_N6; Fanout = 18; REG Node = 'cnt8\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.998 ns" { clk_led cnt8[0] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.25 % ) " "Info: Total cell delay = 2.186 ns ( 29.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.287 ns ( 70.75 % ) " "Info: Total interconnect delay = 5.287 ns ( 70.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.473 ns" { clk_led cnt8[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.473 ns" { clk_led clk_led~out0 cnt8[0] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.737 ns" { clk_led cnt8[2] Mux10~204 Mux10~205 Mux10~206 Mux10~208 Mux19~27 sg[0]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.737 ns" { clk_led clk_led~out0 cnt8[2] Mux10~204 Mux10~205 Mux10~206 Mux10~208 Mux19~27 sg[0]$latch } { 0.000ns 0.000ns 5.287ns 1.849ns 1.651ns 0.768ns 0.182ns 1.221ns 4.881ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.590ns 0.114ns 0.114ns 0.442ns 0.114ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.473 ns" { clk_led cnt8[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.473 ns" { clk_led clk_led~out0 cnt8[0] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.672 ns - Shortest register register " "Info: - Shortest register to register delay is 2.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt8\[0\] 1 REG LC_X12_Y11_N6 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y11_N6; Fanout = 18; REG Node = 'cnt8\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt8[0] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.596 ns) + CELL(0.590 ns) 1.186 ns Mux11~308 2 COMB LC_X12_Y11_N7 8 " "Info: 2: + IC(0.596 ns) + CELL(0.590 ns) = 1.186 ns; Loc. = LC_X12_Y11_N7; Fanout = 8; COMB Node = 'Mux11~308'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.186 ns" { cnt8[0] Mux11~308 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.292 ns) 1.940 ns Mux17~25 3 COMB LC_X12_Y11_N8 1 " "Info: 3: + IC(0.462 ns) + CELL(0.292 ns) = 1.940 ns; Loc. = LC_X12_Y11_N8; Fanout = 1; COMB Node = 'Mux17~25'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.754 ns" { Mux11~308 Mux17~25 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.292 ns) 2.672 ns sg\[0\]\$latch 4 REG LC_X12_Y11_N0 1 " "Info: 4: + IC(0.440 ns) + CELL(0.292 ns) = 2.672 ns; Loc. = LC_X12_Y11_N0; Fanout = 1; REG Node = 'sg\[0\]\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.732 ns" { Mux17~25 sg[0]$latch } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.174 ns ( 43.94 % ) " "Info: Total cell delay = 1.174 ns ( 43.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.498 ns ( 56.06 % ) " "Info: Total interconnect delay = 1.498 ns ( 56.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { cnt8[0] Mux11~308 Mux17~25 sg[0]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { cnt8[0] Mux11~308 Mux17~25 sg[0]$latch } { 0.000ns 0.596ns 0.462ns 0.440ns } { 0.000ns 0.590ns 0.292ns 0.292ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.737 ns" { clk_led cnt8[2] Mux10~204 Mux10~205 Mux10~206 Mux10~208 Mux19~27 sg[0]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.737 ns" { clk_led clk_led~out0 cnt8[2] Mux10~204 Mux10~205 Mux10~206 Mux10~208 Mux19~27 sg[0]$latch } { 0.000ns 0.000ns 5.287ns 1.849ns 1.651ns 0.768ns 0.182ns 1.221ns 4.881ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.590ns 0.114ns 0.114ns 0.442ns 0.114ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.473 ns" { clk_led cnt8[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.473 ns" { clk_led clk_led~out0 cnt8[0] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.475ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { cnt8[0] Mux11~308 Mux17~25 sg[0]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { cnt8[0] Mux11~308 Mux17~25 sg[0]$latch } { 0.000ns 0.596ns 0.462ns 0.440ns } { 0.000ns 0.590ns 0.292ns 0.292ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 150 " "Warning: Circuit may not operate. Detected 150 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "count2\[3\] sg\[5\]\$latch clk 7.899 ns " "Info: Found hold time violation between source  pin or register \"count2\[3\]\" and destination pin or register \"sg\[5\]\$latch\" for clock \"clk\" (Hold time is 7.899 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "11.433 ns + Largest " "Info: + Largest clock skew is 11.433 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 14.203 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 14.203 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns count5\[1\] 2 REG LC_X15_Y10_N2 4 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X15_Y10_N2; Fanout = 4; REG Node = 'count5\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.537 ns" { clk count5[1] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.292 ns) 3.913 ns Mux10~204 3 COMB LC_X15_Y10_N5 1 " "Info: 3: + IC(0.615 ns) + CELL(0.292 ns) = 3.913 ns; Loc. = LC_X15_Y10_N5; Fanout = 1; COMB Node = 'Mux10~204'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.907 ns" { count5[1] Mux10~204 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.651 ns) + CELL(0.590 ns) 6.154 ns Mux10~205 4 COMB LC_X12_Y11_N3 1 " "Info: 4: + IC(1.651 ns) + CELL(0.590 ns) = 6.154 ns; Loc. = LC_X12_Y11_N3; Fanout = 1; COMB Node = 'Mux10~205'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.241 ns" { Mux10~204 Mux10~205 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.114 ns) 7.036 ns Mux10~206 5 COMB LC_X11_Y11_N8 1 " "Info: 5: + IC(0.768 ns) + CELL(0.114 ns) = 7.036 ns; Loc. = LC_X11_Y11_N8; Fanout = 1; COMB Node = 'Mux10~206'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.882 ns" { Mux10~205 Mux10~206 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 7.332 ns Mux10~208 6 COMB LC_X11_Y11_N9 8 " "Info: 6: + IC(0.182 ns) + CELL(0.114 ns) = 7.332 ns; Loc. = LC_X11_Y11_N9; Fanout = 8; COMB Node = 'Mux10~208'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { Mux10~206 Mux10~208 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.442 ns) 8.995 ns Mux19~27 7 COMB LC_X12_Y9_N6 7 " "Info: 7: + IC(1.221 ns) + CELL(0.442 ns) = 8.995 ns; Loc. = LC_X12_Y9_N6; Fanout = 7; COMB Node = 'Mux19~27'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.663 ns" { Mux10~208 Mux19~27 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.916 ns) + CELL(0.292 ns) 14.203 ns sg\[5\]\$latch 8 REG LC_X12_Y9_N3 1 " "Info: 8: + IC(4.916 ns) + CELL(0.292 ns) = 14.203 ns; Loc. = LC_X12_Y9_N3; Fanout = 1; REG Node = 'sg\[5\]\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.208 ns" { Mux19~27 sg[5]$latch } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.248 ns ( 29.91 % ) " "Info: Total cell delay = 4.248 ns ( 29.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.955 ns ( 70.09 % ) " "Info: Total interconnect delay = 9.955 ns ( 70.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.203 ns" { clk count5[1] Mux10~204 Mux10~205 Mux10~206 Mux10~208 Mux19~27 sg[5]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Vie