stopwatch.tan.qmsg

利用Quarteus II 6.0 设计一个秒表

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_led register register cnt8\[1\] cnt8\[1\] 275.03 MHz Internal " "Info: Clock \"clk_led\" Internal fmax is restricted to 275.03 MHz between source register \"cnt8\[1\]\" and destination register \"cnt8\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.993 ns + Longest register register " "Info: + Longest register to register delay is 2.993 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt8\[1\] 1 REG LC_X12_Y11_N2 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y11_N2; Fanout = 18; REG Node = 'cnt8\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt8[1] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.336 ns) + CELL(0.292 ns) 1.628 ns Mux8~342 2 COMB LC_X15_Y11_N2 2 " "Info: 2: + IC(1.336 ns) + CELL(0.292 ns) = 1.628 ns; Loc. = LC_X15_Y11_N2; Fanout = 2; COMB Node = 'Mux8~342'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.628 ns" { cnt8[1] Mux8~342 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.115 ns) 2.993 ns cnt8\[1\] 3 REG LC_X12_Y11_N2 18 " "Info: 3: + IC(1.250 ns) + CELL(0.115 ns) = 2.993 ns; Loc. = LC_X12_Y11_N2; Fanout = 18; REG Node = 'cnt8\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.365 ns" { Mux8~342 cnt8[1] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 13.60 % ) " "Info: Total cell delay = 0.407 ns ( 13.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.586 ns ( 86.40 % ) " "Info: Total interconnect delay = 2.586 ns ( 86.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.993 ns" { cnt8[1] Mux8~342 cnt8[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.993 ns" { cnt8[1] Mux8~342 cnt8[1] } { 0.000ns 1.336ns 1.250ns } { 0.000ns 0.292ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_led destination 7.473 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_led\" to destination register is 7.473 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk_led 1 CLK PIN_122 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 3; CLK Node = 'clk_led'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_led } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(0.711 ns) 7.473 ns cnt8\[1\] 2 REG LC_X12_Y11_N2 18 " "Info: 2: + IC(5.287 ns) + CELL(0.711 ns) = 7.473 ns; Loc. = LC_X12_Y11_N2; Fanout = 18; REG Node = 'cnt8\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.998 ns" { clk_led cnt8[1] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.25 % ) " "Info: Total cell delay = 2.186 ns ( 29.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.287 ns ( 70.75 % ) " "Info: Total interconnect delay = 5.287 ns ( 70.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.473 ns" { clk_led cnt8[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.473 ns" { clk_led clk_led~out0 cnt8[1] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_led source 7.473 ns - Longest register " "Info: - Longest clock path from clock \"clk_led\" to source register is 7.473 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk_led 1 CLK PIN_122 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 3; CLK Node = 'clk_led'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_led } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.287 ns) + CELL(0.711 ns) 7.473 ns cnt8\[1\] 2 REG LC_X12_Y11_N2 18 " "Info: 2: + IC(5.287 ns) + CELL(0.711 ns) = 7.473 ns; Loc. = LC_X12_Y11_N2; Fanout = 18; REG Node = 'cnt8\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.998 ns" { clk_led cnt8[1] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.25 % ) " "Info: Total cell delay = 2.186 ns ( 29.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.287 ns ( 70.75 % ) " "Info: Total interconnect delay = 5.287 ns ( 70.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.473 ns" { clk_led cnt8[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.473 ns" { clk_led clk_led~out0 cnt8[1] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.473 ns" { clk_led cnt8[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.473 ns" { clk_led clk_led~out0 cnt8[1] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.475ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.473 ns" { clk_led cnt8[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.473 ns" { clk_led clk_led~out0 cnt8[1] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.993 ns" { cnt8[1] Mux8~342 cnt8[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.993 ns" { cnt8[1] Mux8~342 cnt8[1] } { 0.000ns 1.336ns 1.250ns } { 0.000ns 0.292ns 0.115ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.473 ns" { clk_led cnt8[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.473 ns" { clk_led clk_led~out0 cnt8[1] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.475ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.473 ns" { clk_led cnt8[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.473 ns" { clk_led clk_led~out0 cnt8[1] } { 0.000ns 0.000ns 5.287ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt8[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { cnt8[1] } {  } {  } } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count1\[3\] register count2\[0\] 178.51 MHz 5.602 ns Internal " "Info: Clock \"clk\" has Internal fmax of 178.51 MHz between source register \"count1\[3\]\" and destination register \"count2\[0\]\" (period= 5.602 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.355 ns + Longest register register " "Info: + Longest register to register delay is 5.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count1\[3\] 1 REG LC_X10_Y10_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N3; Fanout = 3; REG Node = 'count1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count1[3] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.786 ns) + CELL(0.590 ns) 1.376 ns Equal0~49 2 COMB LC_X11_Y10_N1 6 " "Info: 2: + IC(0.786 ns) + CELL(0.590 ns) = 1.376 ns; Loc. = LC_X11_Y10_N1; Fanout = 6; COMB Node = 'Equal0~49'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.376 ns" { count1[3] Equal0~49 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.281 ns) + CELL(0.114 ns) 2.771 ns count2\[1\]~399 3 COMB LC_X11_Y9_N2 4 " "Info: 3: + IC(1.281 ns) + CELL(0.114 ns) = 2.771 ns; Loc. = LC_X11_Y9_N2; Fanout = 4; COMB Node = 'count2\[1\]~399'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.395 ns" { Equal0~49 count2[1]~399 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.717 ns) + CELL(0.867 ns) 5.355 ns count2\[0\] 4 REG LC_X15_Y10_N3 6 " "Info: 4: + IC(1.717 ns) + CELL(0.867 ns) = 5.355 ns; Loc. = LC_X15_Y10_N3; Fanout = 6; REG Node = 'count2\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.584 ns" { count2[1]~399 count2[0] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.571 ns ( 29.34 % ) " "Info: Total cell delay = 1.571 ns ( 29.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.784 ns ( 70.66 % ) " "Info: Total interconnect delay = 3.784 ns ( 70.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { count1[3] Equal0~49 count2[1]~399 count2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.355 ns" { count1[3] Equal0~49 count2[1]~399 count2[0] } { 0.000ns 0.786ns 1.281ns 1.717ns } { 0.000ns 0.590ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.014 ns - Smallest " "Info: - Smallest clock skew is 0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns count2\[0\] 2 REG LC_X15_Y10_N3 6 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y10_N3; Fanout = 6; REG Node = 'count2\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk count2[0] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk count2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 count2[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.768 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns count1\[3\] 2 REG LC_X10_Y10_N3 3 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X10_Y10_N3; Fanout = 3; REG Node = 'count1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.299 ns" { clk count1[3] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { clk count1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { clk clk~out0 count1[3] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk count2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 count2[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { clk count1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { clk clk~out0 count1[3] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.355 ns" { count1[3] Equal0~49 count2[1]~399 count2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.355 ns" { count1[3] Equal0~49 count2[1]~399 count2[0] } { 0.000ns 0.786ns 1.281ns 1.717ns } { 0.000ns 0.590ns 0.114ns 0.867ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk count2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 count2[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { clk count1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { clk clk~out0 count1[3] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk_led 21 " "Warning: Circuit may not operate. Detected 21 non-operational path(s) clocked by clock \"clk_led\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}