stopwatch.tan.qmsg

利用Quarteus II 6.0 设计一个秒表

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "sg\[0\]\$latch " "Warning: Node \"sg\[0\]\$latch\" is a latch" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sg\[1\]\$latch " "Warning: Node \"sg\[1\]\$latch\" is a latch" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sg\[2\]\$latch " "Warning: Node \"sg\[2\]\$latch\" is a latch" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sg\[3\]\$latch " "Warning: Node \"sg\[3\]\$latch\" is a latch" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sg\[4\]\$latch " "Warning: Node \"sg\[4\]\$latch\" is a latch" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sg\[5\]\$latch " "Warning: Node \"sg\[5\]\$latch\" is a latch" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sg\[6\]\$latch " "Warning: Node \"sg\[6\]\$latch\" is a latch" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 115 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_led " "Info: Assuming node \"clk_led\" is an undefined clock" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_led" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 12 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "47 " "Warning: Found 47 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux8~345 " "Info: Detected gated clock \"Mux8~345\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux8~345" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux8~344 " "Info: Detected gated clock \"Mux8~344\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux8~344" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux8~343 " "Info: Detected gated clock \"Mux8~343\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux8~343" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux9~213 " "Info: Detected gated clock \"Mux9~213\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux9~213" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux9~212 " "Info: Detected gated clock \"Mux9~212\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux9~212" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux9~211 " "Info: Detected gated clock \"Mux9~211\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux9~211" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux9~210 " "Info: Detected gated clock \"Mux9~210\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux9~210" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux9~209 " "Info: Detected gated clock \"Mux9~209\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux9~209" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux10~208 " "Info: Detected gated clock \"Mux10~208\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux10~208" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux10~207 " "Info: Detected gated clock \"Mux10~207\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux10~207" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count5\[3\] " "Info: Detected ripple clock \"count5\[3\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count5\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count5\[2\] " "Info: Detected ripple clock \"count5\[2\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count5\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count6\[2\] " "Info: Detected ripple clock \"count6\[2\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count6\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count6\[1\] " "Info: Detected ripple clock \"count6\[1\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count6\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count3\[3\] " "Info: Detected ripple clock \"count3\[3\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count3\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count3\[2\] " "Info: Detected ripple clock \"count3\[2\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count3\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count3\[1\] " "Info: Detected ripple clock \"count3\[1\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count3\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux10~206 " "Info: Detected gated clock \"Mux10~206\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux10~206" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux10~205 " "Info: Detected gated clock \"Mux10~205\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux10~205" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux10~204 " "Info: Detected gated clock \"Mux10~204\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux10~204" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count2\[2\] " "Info: Detected ripple clock \"count2\[2\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count2\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count2\[3\] " "Info: Detected ripple clock \"count2\[3\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count2\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count5\[1\] " "Info: Detected ripple clock \"count5\[1\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count5\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count1\[2\] " "Info: Detected ripple clock \"count1\[2\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count1\[3\] " "Info: Detected ripple clock \"count1\[3\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count2\[1\] " "Info: Detected ripple clock \"count2\[1\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count2\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count1\[1\] " "Info: Detected ripple clock \"count1\[1\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count4\[2\] " "Info: Detected ripple clock \"count4\[2\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count4\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count4\[1\] " "Info: Detected ripple clock \"count4\[1\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count4\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux11~308 " "Info: Detected gated clock \"Mux11~308\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux11~308" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux11~307 " "Info: Detected gated clock \"Mux11~307\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux11~307" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count6\[0\] " "Info: Detected ripple clock \"count6\[0\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count6\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count3\[0\] " "Info: Detected ripple clock \"count3\[0\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count3\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux11~306 " "Info: Detected gated clock \"Mux11~306\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux11~306" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux11~305 " "Info: Detected gated clock \"Mux11~305\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux11~305" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux11~304 " "Info: Detected gated clock \"Mux11~304\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux11~304" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux11~303 " "Info: Detected gated clock \"Mux11~303\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux11~303" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux11~302 " "Info: Detected gated clock \"Mux11~302\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux11~302" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count5\[0\] " "Info: Detected ripple clock \"count5\[0\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count5\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count2\[0\] " "Info: Detected ripple clock \"count2\[0\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux7~103 " "Info: Detected gated clock \"Mux7~103\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux7~103" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count1\[0\] " "Info: Detected ripple clock \"count1\[0\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count4\[0\] " "Info: Detected ripple clock \"count4\[0\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 47 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count4\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Mux8~342 " "Info: Detected gated clock \"Mux8~342\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 32 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Mux8~342" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt8\[1\] " "Info: Detected ripple clock \"cnt8\[1\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt8\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt8\[0\] " "Info: Detected ripple clock \"cnt8\[0\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt8\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt8\[2\] " "Info: Detected ripple clock \"cnt8\[2\]\" as buffer" {  } { { "stopwatch.vhd" "" { Text "E:/EDA programming/work/stopwatch/stopwatch.vhd" 111 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt8\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}